de2_ccd_detect.tan.rpt

来自「DC2的用户手册」· RPT 代码 · 共 210 行 · 第 1/5 页

; Cut off feedback from I/O pins                        ; On                 ;                 ;                         ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;                 ;                         ;             ;
; Ignore Clock Settings                                 ; Off                ;                 ;                         ;             ;
; Analyze latches as synchronous elements               ; On                 ;                 ;                         ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;                 ;                         ;             ;
; Enable Clock Latency                                  ; Off                ;                 ;                         ;             ;
; Clock Settings                                        ; Ccd Pixclk         ;                 ; GPIO_1[10]              ;             ;
; Clock Settings                                        ; Ccd Mclk           ;                 ; GPIO_1[11]              ;             ;
; Clock Settings                                        ; Ccd Pixclk         ;                 ; GPIO_1[30]              ;             ;
; Clock Settings                                        ; Ccd Mclk           ;                 ; GPIO_1[31]              ;             ;
; Cut Timing Path                                       ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe6|dffe7a ; dcfifo_7lb1 ;
; Cut Timing Path                                       ; On                 ; rdptr_g         ; ws_dgrp|dffpipe8|dffe9a ; dcfifo_7lb1 ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                                           ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 2                     ; 1                   ; -2.368 ns ;              ;
; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 2                     ; 1                   ; -5.368 ns ;              ;
; Audio_PLL:u10|altpll:altpll_component|_clk0                               ;                    ; PLL output ; 18.41 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_27 ; 15                    ; 22                  ; -2.394 ns ;              ;
; GPIO_1[10]                                                                ; CCD_PIXCLK         ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_1[30]                                                                ; CCD_PIXCLK         ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_1[31]                                                                ; CCD_MCLK           ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_1[11]                                                                ; CCD_MCLK           ; User Pin   ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; CLOCK_50                                                                  ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; CLOCK_27                                                                  ;                    ; User Pin   ; 27.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                         ; To                                ; From Clock                                                                ; To Clock                                                                  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 2.809 ns                                ; 139.06 MHz ( period = 7.191 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1] ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.747 ns                  ; 6.938 ns                ;
; 2.840 ns                                ; 139.66 MHz ( period = 7.160 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[5] ; Sdram_Control_4Port:u6|mADDR[21]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.746 ns                  ; 6.906 ns                ;
; 2.984 ns                                ; 142.53 MHz ( period = 7.016 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1] ; Sdram_Control_4Port:u6|mADDR[8]   ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.775 ns                  ; 6.791 ns                ;
; 2.984 ns                                ; 142.53 MHz ( period = 7.016 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1] ; Sdram_Control_4Port:u6|mADDR[14]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.780 ns                  ; 6.796 ns                ;
; 2.984 ns                                ; 142.53 MHz ( period = 7.016 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1] ; Sdram_Control_4Port:u6|mADDR[16]  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.780 ns                  ; 6.796 ns                ;