de2_ccd_detect.tan.rpt

DC2的用户手册

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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+------------------------------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------+------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Type                                                                                     ; Slack     ; Required Time                     ; Actual Time                      ; From                                                                                                                         ; To                                 ; From Clock                                                                ; To Clock                                                                  ; Failed Paths ;
+------------------------------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------+------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Worst-case tsu                                                                           ; N/A       ; None                              ; 6.941 ns                         ; DRAM_DQ[2]                                                                                                                   ; Sdram_Control_4Port:u6|mDATAOUT[2] ; --                                                                        ; CLOCK_50                                                                  ; 0            ;
; Worst-case tco                                                                           ; N/A       ; None                              ; 16.367 ns                        ; Y                                                                                                                            ; VGA_R[0]                           ; CLOCK_50                                                                  ; --                                                                        ; 0            ;
; Worst-case tpd                                                                           ; N/A       ; None                              ; 10.310 ns                        ; SW[15]                                                                                                                       ; LEDR[15]                           ; --                                                                        ; --                                                                        ; 0            ;
; Worst-case th                                                                            ; N/A       ; None                              ; 3.707 ns                         ; SW[4]                                                                                                                        ; I2C_CCD_Config:u7|mI2C_DATA[4]     ; --                                                                        ; CLOCK_50                                                                  ; 0            ;
; Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0' ; 2.809 ns  ; 100.00 MHz ( period = 10.000 ns ) ; 139.06 MHz ( period = 7.191 ns ) ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[1] ; Sdram_Control_4Port:u6|mADDR[21]   ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'CLOCK_50'                                                                  ; 11.745 ns ; 50.00 MHz ( period = 20.000 ns )  ; 121.14 MHz ( period = 8.255 ns ) ; Y                                                                                                                            ; DLY_cont[17]                       ; CLOCK_50                                                                  ; CLOCK_50                                                                  ; 0            ;
; Clock Setup: 'GPIO_1[10]'                                                                ; 34.462 ns ; 25.00 MHz ( period = 40.000 ns )  ; 180.57 MHz ( period = 5.538 ns ) ; CCD_Capture:u3|Y_Cont[0]                                                                                                     ; RAW2RGB:u4|mCCD_G[10]              ; GPIO_1[10]                                                                ; GPIO_1[10]                                                                ; 0            ;
; Clock Setup: 'Audio_PLL:u10|altpll:altpll_component|_clk0'                               ; 51.782 ns ; 18.41 MHz ( period = 54.320 ns )  ; 394.01 MHz ( period = 2.538 ns ) ; AUDIO_DAC:u9|LRCK_1X_DIV[1]                                                                                                  ; AUDIO_DAC:u9|LRCK_1X_DIV[8]        ; Audio_PLL:u10|altpll:altpll_component|_clk0                               ; Audio_PLL:u10|altpll:altpll_component|_clk0                               ; 0            ;
; Clock Hold: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'  ; 0.391 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; Sdram_Control_4Port:u6|ST[0]                                                                                                 ; Sdram_Control_4Port:u6|ST[0]       ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'Audio_PLL:u10|altpll:altpll_component|_clk0'                                ; 0.391 ns  ; 18.41 MHz ( period = 54.320 ns )  ; N/A                              ; AUDIO_DAC:u9|LRCK_1X                                                                                                         ; AUDIO_DAC:u9|LRCK_1X               ; Audio_PLL:u10|altpll:altpll_component|_clk0                               ; Audio_PLL:u10|altpll:altpll_component|_clk0                               ; 0            ;
; Clock Hold: 'GPIO_1[10]'                                                                 ; 0.391 ns  ; 25.00 MHz ( period = 40.000 ns )  ; N/A                              ; CCD_Capture:u3|mSTART                                                                                                        ; CCD_Capture:u3|mSTART              ; GPIO_1[10]                                                                ; GPIO_1[10]                                                                ; 0            ;
; Clock Hold: 'CLOCK_50'                                                                   ; 0.391 ns  ; 50.00 MHz ( period = 20.000 ns )  ; N/A                              ; Reset_Delay:u2|oRST_1                                                                                                        ; Reset_Delay:u2|oRST_1              ; CLOCK_50                                                                  ; CLOCK_50                                                                  ; 0            ;
; Total number of failed paths                                                             ;           ;                                   ;                                  ;                                                                                                                              ;                                    ;                                                                           ;                                                                           ; 0            ;
+------------------------------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------+------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                             ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+
; Option                                                ; Setting            ; From            ; To                      ; Entity Name ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+
; Device Name                                           ; EP2C35F672C6       ;                 ;                         ;             ;
; Timing Models                                         ; Preliminary        ;                 ;                         ;             ;
; Number of source nodes to report per destination node ; 10                 ;                 ;                         ;             ;
; Number of destination nodes to report                 ; 10                 ;                 ;                         ;             ;
; Number of paths to report                             ; 200                ;                 ;                         ;             ;
; Report Minimum Timing Checks                          ; Off                ;                 ;                         ;             ;
; Use Fast Timing Models                                ; Off                ;                 ;                         ;             ;
; Report IO Paths Separately                            ; Off                ;                 ;                         ;             ;
; Default hold multicycle                               ; Same As Multicycle ;                 ;                         ;             ;
; Cut paths between unrelated clock domains             ; On                 ;                 ;                         ;             ;
; Cut off read during write signal paths                ; On                 ;                 ;                         ;             ;