isp8_io_cntl.vhd

Lattice 超精简8位软核CPU--Mico8

------------------------------------------------------------------------------
-- 
--  Name:   isp8_io_cntl.vhd
-- 
--  Description:  Input/Output control logic
-- 
--  $Revision: 1.2 $
--  
------------------------------------------------------------------------------
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
------------------------------------------------------------------------------
--
--    Lattice Semiconductor Corporation
--    5555 NE Moore Court
--    Hillsboro, OR 97124
--    U.S.A
--
--    TEL: 1-800-Lattice (USA and Canada)
--    408-826-6000 (other locations)
--
--    web: http://www.latticesemi.com/
--    email: [e-mail]
-- 
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity isp8_io_cntl is
    generic(PORT_AW             : natural := 8);
    port(clk          : in  std_logic;
         rst_n        : in  std_logic;
         import       : in  std_logic;
         importi      : in  std_logic;
         export       : in  std_logic;
         exporti      : in  std_logic;
         ssp          : in  std_logic;
         sspi         : in  std_logic;
         lsp          : in  std_logic;
         lspi         : in  std_logic;
         addr_cyc     : in  std_logic;
         ext_addr_cyc : in  std_logic;
         addr_rb      : in  std_logic_vector(4 downto 0);
         dout_rd      : in  std_logic_vector(7 downto 0);
         dout_rb      : in  std_logic_vector(7 downto 0);
         ext_addr     : out std_logic_vector((PORT_AW - 1) downto 0);
         ext_dout     : out std_logic_vector(7 downto 0);
         ext_mem_wr   : out std_logic;
         ext_mem_rd   : out std_logic;
         ext_io_wr    : out std_logic;
         ext_io_rd    : out std_logic);
end isp8_io_cntl;


architecture behave of isp8_io_cntl is
begin

    process(clk, rst_n)
    begin
	if (rst_n = '0') then
            ext_dout <= "00000000";
            ext_io_wr <= '0';
            ext_io_rd <= '0';
	elsif rising_edge(clk) then
            ext_dout <= dout_rd;
            ext_io_wr <= (export OR exporti) AND (addr_cyc or ext_addr_cyc);
            ext_io_rd <= (import OR importi) AND (addr_cyc or ext_addr_cyc);
	end if;
    end process;

    process(clk, rst_n)
    begin
	if (rst_n = '0') then
            ext_addr <= (others => '0');
	elsif rising_edge(clk) then
            if ((export = '1') OR (import = '1') or (lsp = '1') or (ssp = '1')) then
                ext_addr <= "000" & addr_rb;
            else
                ext_addr <= dout_rb((PORT_AW - 1) downto 0);
            end if;
	end if;
    end process;

    process(clk, rst_n)
    begin
       if (rst_n = '0') then
          ext_mem_wr <= '0';
          ext_mem_rd <= '0';
       elsif rising_edge(clk) then
          ext_mem_wr <= (sspi or ssp) AND (addr_cyc or ext_addr_cyc);
          ext_mem_rd <= (lspi or lsp) AND (addr_cyc or ext_addr_cyc);
       end if;
    end process;

end behave;

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