syscntrl.vhd

Lattice 超精简8位软核CPU--Mico8

-- SysCntrl.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--           
--                     Lattice Semiconductor Corporation
--                     5555 NE Moore Court
--                     Hillsboro, OR 97214
--                     U.S.A
--
--                     TEL: 1-800-Lattice (USA and Canada)
--                          408-826-6000 (other locations)
--
--                     web: http://www.latticesemi.com/
--                     email: [e-mail]
--
-- --------------------------------------------------------------------
--
-- This is low level control and init unit
--
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
--   Ver  :| Author            :| Mod. Date :| Changes Made:
--   V1.0 :| G.M.              :| 15/03/06  :| Release
-- ------------------------------------------------------------------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity Sys_Cntrl is
  	port 
	(
		nReset: in std_logic;
--		Clk: in std_logic;
--		SW: in std_logic;
--		INT_Ack: in std_logic;
--		Mico_Addr: in std_logic_vector(7 downto 0);
--		RD: in std_logic;	
--		WR: in std_logic;
		Reset: out std_logic;
		RC5_PWR: out std_logic;
		One: out std_logic;
		Zero: out std_logic

	);
end Sys_Cntrl;

architecture behaviour of Sys_Cntrl is

begin

Zero <= '0';
One <= '1';
RC5_PWR <= '1';
Reset <= NOT nReset; -- no reset

end behaviour;