mico8.vht

Lattice 超精简8位软核CPU--Mico8

-- VHDL test bench created from symbol mico8.sym -- Mar 14 09:24:58 2008

library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library ecp2;
use ecp2.components.all;
-- synopsys translate_on

entity testbench is
end testbench;

Architecture behavior of testbench is

   signal  Mico_WR : std_logic;
   signal  PeriCLK : std_logic;
   signal   CLK_IN : std_logic;
   signal   INTAck : std_logic;
   signal  Mico_RD : std_logic;
   signal Mico_Int : std_logic;
   signal   nReset : std_logic;
   signal  Ser_Out : std_logic;
   signal    Valid : std_logic;
   signal     LEDs : std_logic_vector (7 downto 0);
   signal      PWM : std_logic;
   signal      TXD : std_logic;
   signal   LCD_EN : std_logic;
   signal    LCD_D : std_logic_vector (7 downto 0);
   signal   LCD_RS : std_logic;
   signal  RC5_PWR : std_logic;
   signal    Segm1 : std_logic_vector (6 downto 0);
   signal    Segm2 : std_logic_vector (6 downto 0);
   signal   RC5_IN : std_logic;
   signal     DIP8 : std_logic_vector (7 downto 0);
   signal      RXD : std_logic;

   component MICO8
      Port ( Mico_WR : Out   std_logic;
             PeriCLK : Out   std_logic;
              CLK_IN : In    std_logic;
              INTAck : Out   std_logic;
             Mico_RD : Out   std_logic;
             Mico_Int : Out   std_logic;
              nReset : In    std_logic;
             Ser_Out : Out   std_logic;
               Valid : Out   std_logic;
                LEDs : Out   std_logic_vector (7 downto 0);
                 PWM : Out   std_logic;
                 TXD : Out   std_logic;
              LCD_EN : Out   std_logic;
               LCD_D : Out   std_logic_vector (7 downto 0);
              LCD_RS : Out   std_logic;
             RC5_PWR : Out   std_logic;
               Segm1 : Out   std_logic_vector (6 downto 0);
               Segm2 : Out   std_logic_vector (6 downto 0);
              RC5_IN : In    std_logic;
                DIP8 : In    std_logic_vector (7 downto 0);
                 RXD : In    std_logic );
   end component;

begin
   UUT : MICO8
      Port Map ( CLK_IN=>CLK_IN, DIP8=>DIP8, INTAck=>INTAck,
                 LCD_D=>LCD_D, LCD_EN=>LCD_EN, LCD_RS=>LCD_RS,
                 LEDs=>LEDs, Mico_Int=>Mico_Int, Mico_RD=>Mico_RD,
                 Mico_WR=>Mico_WR, nReset=>nReset, PeriCLK=>PeriCLK,
                 PWM=>PWM, RC5_IN=>RC5_IN, RC5_PWR=>RC5_PWR, RXD=>RXD,
                 Segm1=>Segm1, Segm2=>Segm2, Ser_Out=>Ser_Out, TXD=>TXD,
                 Valid=>Valid );

-- *** Test Bench - User Defined Section ***
   TB : process
   begin
      wait; -- will wait forever
   end process;
-- *** End Test Bench - User Defined Section ***

end behavior;