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PLL/DLL Summary
---------------
PLL 1: Pin/Node Value
PLL Instance Name: I47/PLLDInst_0
PLL Type: EHXPLLD
Input Clock: PIN CLK_IN_c
Output Clock(P): PIN X2CLK_c
Output Clock(S): NONE
Output Clock(K): NODE MicoCLK
PLL Feedback Signal: NODE I47/CLKFB_t
PLL Reset Signal: NODE nReset_c_i
PLL K Divider Reset Signal: NODE GND
PLL LOCK Signal: NONE
Dynamic Delay Mode Signal: NONE
Dynamic Delay Zero Signal: NONE
Dynamic Delay Lag/Lead Select: NONE
Dynamic Delay 0: NONE
Dynamic Delay 1: NONE
Dynamic Delay 2: NONE
Dynamic Phase Adjust Mode Signal: NONE
Dynamic Phase Adjust Input 0: NONE
Dynamic Phase Adjust Input 1: NONE
Dynamic Phase Adjust Input 2: NONE
Dynamic Phase Adjust Input 3: NONE
Dynamic Duty Adjust Input 0: NONE
Dynamic Duty Adjust Input 1: NONE
Dynamic Duty Adjust Input 2: NONE
Dynamic Duty Adjust Input 3: NONE
Input Clock Frequency (MHz): 25.0000
Output Clock(P) Frequency (MHz): 100.0000
Output Clock(K) Frequency (MHz): 50.0000
Output Clock(P) Actual Frequency: 100.000000
Output Clock(P) Frequency Tolerance: NONE
CLKOP BYPASS: DISABLED
CLKOS BYPASS: DISABLED
CLKOK BYPASS: DISABLED
CLKI Divider: 1
CLKFB Divider: 4
CLKOP Divider: 8
CLKOK Divider: 2
PLL Delay Factor (*130ps): 0
CLKOS Phase Shift (degree): 0.0
CLKOS Duty Cycle (*1/16): 8
Delay Control: STATIC
Phase Control: STATIC
FB_MODE: NONE
<A name="mrp_sym"></A><B><U><big>Symbol Cross Reference</big></U></B>
I70/SLICE_0 (PFU) covers blocks: I70/duty_cyle_op_ge_op_ge_un2_counter_cry_7_0
I70/SLICE_1 (PFU) covers blocks: I70/duty_cyle_op_ge_op_ge_un2_counter_cry_5_0
I70/SLICE_2 (PFU) covers blocks: I70/duty_cyle_op_ge_op_ge_un2_counter_cry_3_0
I70/SLICE_3 (PFU) covers blocks: I70/duty_4, I70/duty_5,
I70/duty_cyle_op_ge_op_ge_un2_counter_cry_1_0
I70/SLICE_4 (PFU) covers blocks: I70/duty_2, I70/duty_3,
I70/duty_cyle_op_ge_op_ge_un2_counter_cry_0_0
I70/SLICE_5 (PFU) covers blocks: I70/counter_7, I70/counter_s_0_7
I70/SLICE_6 (PFU) covers blocks: I70/counter_5, I70/counter_6,
I70/counter_cry_0_5
I70/SLICE_7 (PFU) covers blocks: I70/counter_3, I70/counter_4,
I70/counter_cry_0_3
I70/SLICE_8 (PFU) covers blocks: I70/counter_1, I70/counter_2,
I70/counter_cry_0_1
I70/SLICE_9 (PFU) covers blocks: I70/counter_0, I70/counter_cry_0_0
I72/SLICE_10 (PFU) covers blocks: I72/timecounter_12,
I72/un6_timecounter_cry_11_0
I72/SLICE_11 (PFU) covers blocks: I72/timecounter_10,
I72/un6_timecounter_cry_9_0
I72/SLICE_12 (PFU) covers blocks: I72/un6_timecounter_cry_7_0
I72/SLICE_13 (PFU) covers blocks: I72/timecounter_6, I72/un6_timecounter_cry_5_0
I72/SLICE_14 (PFU) covers blocks: I72/timecounter_4, I72/un6_timecounter_cry_3_0
I72/SLICE_15 (PFU) covers blocks: I72/timecounter_1, I72/timecounter_2,
I72/un6_timecounter_cry_1_0
I72/SLICE_16 (PFU) covers blocks: I72/un6_timecounter_cry_0_0
I75/SLICE_17 (PFU) covers blocks: I75/PER1_REG_0, I75/PER1_REG_1,
I75/count_cry_0_3
I75/SLICE_18 (PFU) covers blocks: I75/PER0_REG_2, I75/PER0_REG_3,
I75/count_cry_0_1
I75/SLICE_19 (PFU) covers blocks: I75/PER0_REG_0, I75/PER0_REG_1,
I75/count_cry_0_0
I76/SLICE_20 (PFU) covers blocks: I76/Data_Out_4, I76/Data_Out_5,
I76/DIP_Check_un1_prev_state_0_I_28_0
I76/SLICE_21 (PFU) covers blocks: I76/Data_Out_0, I76/Data_Out_1,
I76/DIP_Check_un1_prev_state_0_I_10_0
I76/SLICE_22 (PFU) covers blocks: I76/Data_Out_2, I76/Data_Out_3,
I76/DIP_Check_un1_prev_state_0_I_1_0
I77/SLICE_23 (PFU) covers blocks: I77/Data_Out_4, I77/Data_Out_5,
I77/timecounter_cry_0_11
I77/SLICE_24 (PFU) covers blocks: I77/Data_Out_reg_7, I77/Data_Out_reg_8,
I77/timecounter_cry_0_9
I77/SLICE_25 (PFU) covers blocks: I77/Data_Out_reg_5, I77/Data_Out_reg_6,
I77/timecounter_cry_0_7
I77/SLICE_26 (PFU) covers blocks: I77/Data_Out_reg_3, I77/Data_Out_reg_4,
I77/timecounter_cry_0_5
I77/SLICE_27 (PFU) covers blocks: I77/Data_Out_reg_1, I77/Data_Out_reg_2,
I77/timecounter_cry_0_3
I77/SLICE_28 (PFU) covers blocks: I77/Data_Out_2, I77/Data_Out_3,
I77/timecounter_cry_0_1
I77/SLICE_29 (PFU) covers blocks: I77/Data_Out_0, I77/Data_Out_1,
I77/timecounter_cry_0_0
I79/SLICE_30 (PFU) covers blocks: I79/Data_Out_0, I79/Data_Out_1,
I79/timecounter_cry_0_0
I79/SLICE_31 (PFU) covers blocks: I79/Data_Out_4, I79/Data_Out_5,
I79/timecounter_cry_0_11
I79/SLICE_32 (PFU) covers blocks: I79/Data_Out_reg_7, I79/Data_Out_reg_8,
I79/timecounter_cry_0_9
I79/SLICE_33 (PFU) covers blocks: I79/Data_Out_reg_5, I79/Data_Out_reg_6,
I79/timecounter_cry_0_7
I79/SLICE_34 (PFU) covers blocks: I79/Data_Out_reg_3, I79/Data_Out_reg_4,
I79/timecounter_cry_0_5
I79/SLICE_35 (PFU) covers blocks: I79/Data_Out_reg_1, I79/Data_Out_reg_2,
I79/timecounter_cry_0_3
I79/SLICE_36 (PFU) covers blocks: I79/Data_Out_2, I79/Data_Out_3,
I79/timecounter_cry_0_1
I78/u1_isp8/u1_isp8_flow_cntl/SLICE_37 (PFU) covers blocks:
I78/u1_isp8/u1_isp8_flow_cntl/pc_int_cry_7_0
I78/u1_isp8/u1_isp8_flow_cntl/SLICE_38 (PFU) covers blocks:
I78/u1_isp8/u1_isp8_flow_cntl/pc_int_cry_5_0
I78/u1_isp8/u1_isp8_flow_cntl/SLICE_39 (PFU) covers blocks:
I78/u1_isp8/u1_isp8_flow_cntl/intr_reg0$r31,
I78/u1_isp8/u1_isp8_flow_cntl/intr_reg0$r69,
I78/u1_isp8/u1_isp8_flow_cntl/pc_int_cry_3_0
I78/u1_isp8/u1_isp8_flow_cntl/SLICE_40 (PFU) covers blocks:
I78/u1_isp8/u1_isp8_flow_cntl/addr_jmp_reg_5,
I78/u1_isp8/u1_isp8_flow_cntl/addr_jmp_reg_8,
I78/u1_isp8/u1_isp8_flow_cntl/pc_int_cry_1_0
I78/u1_isp8/u1_isp8_flow_cntl/SLICE_41 (PFU) covers blocks:
I78/u1_isp8/u1_isp8_flow_cntl/intr_ack_int,
I78/u1_isp8/u1_isp8_flow_cntl/pc_int_cry_0_0
I78/u1_isp8/u1_isp8_alu/u1_addsub8/SLICE_42 (PFU) covers blocks:
I78/u1_isp8/u1_isp8_alu/u1_addsub8/addsub_4
I78/u1_isp8/u1_isp8_alu/u1_addsub8/SLICE_43 (PFU) covers blocks:
I78/u1_isp8/u1_isp8_alu/u1_addsub8/addsub_0
I78/u1_isp8/SLICE_44 (PFU) covers blocks: I78/u1_isp8/din_rd1_1$r65,
I78/u1_isp8/din_rd1_2$r62, I78/u1_isp8/u1_isp8_alu/u1_addsub8/addsub_1
I78/u1_isp8/SLICE_45 (PFU) covers blocks: I78/u1_isp8/din_rd1_3$r59,
I78/u1_isp8/din_rd1_4$r56, I78/u1_isp8/u1_isp8_alu/u1_addsub8/addsub_2
I78/u1_isp8/SLICE_46 (PFU) covers blocks: I78/u1_isp8/din_rd1_5$r53,
I78/u1_isp8/din_rd1_6$r50, I78/u1_isp8/u1_isp8_alu/u1_addsub8/addsub_3
I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2/SLICE_47 (PFU) covers
blocks: I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2/RAMW
I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2/SLICE_48 (PFU) covers
blocks: I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2/RAM0
I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2/SLICE_49 (PFU) covers
blocks: I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_2/RAM2
I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0/SLICE_50 (PFU) covers
blocks: I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0/RAMW
I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0/SLICE_51 (PFU) covers
blocks: I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0/RAM0
I78/u1_isp8/u1_isp8_flow_cntl/SLICE_52 (PFU) covers blocks:
I78/u1_isp8/u1_isp8_flow_cntl/carry_flag_int$r3,
I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_0/RAM2
I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_1/SLICE_53 (PFU) covers
blocks: I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_1/RAMW
I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_1/SLICE_54 (PFU) covers
blocks: I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_1/RAM0
I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_1/SLICE_55 (PFU) covers
blocks: I78/u1_isp8/u1_isp8_flow_cntl/u1_isp8_stkmem/mem_0_1/RAM2
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_1_1/SLICE_56 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_1_1/RAMW
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_1_1/SLICE_57 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_1_1/RAM0
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_1_1/SLICE_58 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_1_1/RAM2
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_0_0/SLICE_59 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_0_0/RAMW
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_0_0/SLICE_60 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_0_0/RAM0
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_0_0/SLICE_61 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_0_0/RAM2
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_0_1/SLICE_62 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_0_1/RAMW
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_0_1/SLICE_63 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_0_1/RAM0
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_0_1/SLICE_64 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_0_1/RAM2
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_1_0/SLICE_65 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_1_0/RAMW
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_1_0/SLICE_66 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_1_0/RAM0
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_1_0/SLICE_67 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/mem_1_0/RAM2
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_1_1/SLICE_68 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_1_1/RAMW
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_1_1/SLICE_69 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_1_1/RAM0
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_1_1/SLICE_70 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_1_1/RAM2
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_0/SLICE_71 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_0/RAMW
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_0/SLICE_72 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_0/RAM0
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_0/SLICE_73 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_0/RAM2
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/SLICE_74 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/RAMW
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/SLICE_75 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/RAM0
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/SLICE_76 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/RAM2
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_1_0/SLICE_77 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_1_0/RAMW
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_1_0/SLICE_78 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_1_0/RAM0
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_1_0/SLICE_79 (PFU) covers blocks:
I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_1_0/RAM2
I78/U2_scratchpad/mem_1_1/SLICE_80 (PFU) covers blocks:
I78/U2_scratchpad/mem_1_1/RAMW
I78/U2_scratchpad/mem_1_1/SLICE_81 (PFU) covers blocks:
I78/U2_scratchpad/mem_1_1/RAM0
I78/U2_scratchpad/mem_1_1/SLICE_82 (PFU) covers blocks:
I78/U2_scratchpad/mem_1_1/RAM2
I78/U2_scratchpad/mem_0_0/SLICE_83 (PFU) covers blocks:
I78/U2_scratchpad/mem_0_0/RAMW
I78/U2_scratchpad/mem_0_0/SLICE_84 (PFU) covers blocks:
I78/U2_scratchpad/mem_0_0/RAM0
I78/U2_scratchpad/mem_0_0/SLICE_85 (PFU) covers blocks:
I78/U2_scratchpad/mem_0_0/RAM2
I78/U2_scratchpad/mem_0_1/SLICE_86 (PFU) covers blocks:
I78/U2_scratchpad/mem_0_1/RAMW
I78/U2_scratchpad/mem_0_1/SLICE_87 (PFU) covers blocks:
I78/U2_scratchpad/mem_0_1/RAM0
I78/U2_scratchpad/mem_0_1/SLICE_88 (PFU) covers blocks:
I78/U2_scratchpad/mem_0_1/RAM2
I78/U2_scratchpad/mem_1_0/SLICE_89 (PFU) covers blocks:
I78/U2_scratchpad/mem_1_0/RAMW
I78/U2_scratchpad/mem_1_0/SLICE_90 (PFU) covers blocks:
I78/U2_scratchpad/mem_1_0/RAM0
I78/U2_scratchpad/mem_1_0/SLICE_91 (PFU) covers blocks:
I78/U2_scratchpad/mem_1_0/RAM2
I65/SLICE_94 (PFU) covers blocks: I65/serializer_addr_2, I65/dserdata_4,
I65/dserdata_5
I65/SLICE_95 (PFU) covers blocks: I65/un3_ser_out_c2,
I65/serializer_txdata8_5_i, I65/dserdata_6, I65/dserdata_7
I65/SLICE_96 (PFU) covers blocks: I65/serializer_shift_cnt_5_0,
I65/serializer_dserdata8, I65/shift_cnt_0
I65/SLICE_97 (PFU) covers blocks: I65/serializer_shift_cnt_5_1,
I65/serializer_shift_cnt_5_2, I65/shift_cnt_1, I65/shift_cnt_2
I65/SLICE_98 (PFU) covers blocks: I65/serializer_N_30_i,
I65/serializer_un1_ser_out_i, I65/shift_cnt_3
I70/SLICE_102 (PFU) covers blocks: I70/duty_0_sqmuxa_0_a2,
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