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<HEAD><TITLE>Map Report</TITLE>
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<A name="Mrp"></A> Lattice Mapping Report File for Design 'MICO8'
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
Command line: C:\Tools\Lattice\ispTOOLS7_0\ispfpga\bin\nt\map.exe -a
LatticeECP2 -p LFE2-6E -t TQFP144 -s 7 mico8.ngd -o mico8_map.ncd -mp
mico8.mrp mico8.lpf -c 0 -m -retime EFFORT=5:DETOUR=5 -tdm -split_node
-td_pack
Target Vendor: LATTICE
Target Device: LFE2-6ETQFP144
Target Speed: 7
Mapper: ep5a00, version: ispLever_v70_SP2_Build (24)
Mapped on: 03/14/08 11:43:15
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
Number of registers: 345
PFU registers: 313
PIO registers: 32
Number of SLICEs: 359 out of 3024 (12%)
SLICEs(logic/ROM): 314 out of 2457 (13%)
SLICEs(logic/ROM/RAM): 45 out of 567 (8%)
As RAM: 45 out of 567 (8%)
As Logic/ROM: 0 out of 567 (0%)
Number of logic LUT4s: 484
Number of distributed RAM: 45 (90 LUT4s)
Number of ripple logic: 47 (94 LUT4s)
Number of shift registers: 0
Total number of LUT4s: 668
Number of external PIOs: 54 out of 90 (60%)
Number of PIO IDDR/ODDR: 0
Number of PIO FIXEDDELAY: 0
Number of DQSDLLs: 0 out of 2 (0%)
Number of 3-state buffers: 0
Number of PLLs: 1 out of 2 (50%)
Number of DLLs: 0 out of 2 (0%)
Number of block RAMs: 1 out of 3 (33%)
Number of CLKDIVs: 0 out of 2 (0%)
Number of GSRs: 1 out of 1 (100%)
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
DSP Component Details --
------------------------
Number Of Mapped DSP Components:
--------------------------------
MULT36X36B 0
MULT18X18B 0
MULT18X18MACB 0
MULT18X18ADDSUBB 0
MULT18X18ADDSUBSUMB 0
MULT9X9B 0
MULT9X9ADDSUBB 0
MULT9X9ADDSUBSUMB 0
--------------------------------
Number of clocks: 1
Net MicoCLK: 256 loads, 256 rising, 0 falling (Driver: I47/PLLDInst_0 )
Number of Clock Enables: 34
Net I72_txdata8_5_i: 2 loads, 0 LSLICEs
Net N_41_i: 1 loads, 0 LSLICEs
Net I78_u1_isp8_u1_isp8_flow_cntl_data_cyc_int: 7 loads, 5 LSLICEs
Net I65/un1_ser_out_1_i_0: 3 loads, 3 LSLICEs
Net I65/dserdata_0_sqmuxa: 4 loads, 4 LSLICEs
Net I70/duty_0_sqmuxa: 4 loads, 4 LSLICEs
Net I69_LEDs_Out_0_sqmuxa: 8 loads, 0 LSLICEs
Net I72/StartSending_1_sqmuxa_i: 1 loads, 1 LSLICEs
Net TxState_14: 2 loads, 1 LSLICEs
Net I72/txdata8: 4 loads, 4 LSLICEs
Net I72/N_86_i: 4 loads, 4 LSLICEs
Net I71_LCD_Enable_1_sqmuxa: 2 loads, 0 LSLICEs
Net I71_LCD_Data_0_sqmuxa: 8 loads, 0 LSLICEs
Net I74/Leds_out_0_sqmuxa: 4 loads, 4 LSLICEs
Net I75/N_274_i: 3 loads, 3 LSLICEs
Net I75/un1_per2_reg12_i_s_0: 4 loads, 4 LSLICEs
Net I75/un1_per1_reg12_i_s_0: 4 loads, 4 LSLICEs
Net I75/un1_per0_reg12_i_s_0: 4 loads, 4 LSLICEs
Net I75/un1_Mico8_INT_1_sqmuxa_1_0_i: 1 loads, 1 LSLICEs
Net I75/INT_REG_0_sqmuxa_i_s: 3 loads, 3 LSLICEs
Net I76/Data_Out_0_sqmuxa: 4 loads, 4 LSLICEs
Net I77/buffer_empty_1_sqmuxa_i: 1 loads, 1 LSLICEs
Net I77/un1_timecounter_pulse_0_a2_0: 7 loads, 7 LSLICEs
Net I77/N_139_i: 1 loads, 1 LSLICEs
Net I77/un17_timecounter_pulse_0_a2_0: 4 loads, 4 LSLICEs
Net I79/un1_timecounter_pulse_0_a2: 7 loads, 7 LSLICEs
Net I79/buffer_empty_1_sqmuxa_i: 1 loads, 1 LSLICEs
Net I79/N_139_i: 1 loads, 1 LSLICEs
Net I79/un17_timecounter_pulse_0_a2: 4 loads, 4 LSLICEs
Net I78/u1_isp8/addr_cyc: 9 loads, 9 LSLICEs
Net I78/u1_isp8/u1_isp8_flow_cntl/N_285_i: 1 loads, 1 LSLICEs
Net I78/u1_isp8/u1_isp8_flow_cntl/N_20: 1 loads, 1 LSLICEs
Net I78/u1_isp8/u1_isp8_flow_cntl/N_287_i: 1 loads, 1 LSLICEs
Net I78/u1_isp8/u1_isp8_flow_cntl/N_286_i: 7 loads, 7 LSLICEs
Number of LSRs: 9
Net un1_reset_1: 1 loads, 1 LSLICEs
Net un1_reset: 1 loads, 1 LSLICEs
Net I78/u1_isp8/u1_isp8_flow_cntl/N_22: 3 loads, 3 LSLICEs
Net I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/dec_wre7: 2 loads, 2 LSLICEs
Net I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/dec_wre3: 2 loads, 2 LSLICEs
Net I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/dec_wre7: 2 loads, 2 LSLICEs
Net I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/dec_wre3: 2 loads, 2 LSLICEs
Net I78/U2_scratchpad/dec_wre7: 2 loads, 2 LSLICEs
Net I78/U2_scratchpad/dec_wre3: 2 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net VCC: 74 loads
Net MicoAddr_1: 46 loads
Net MicoAddr_0: 45 loads
Net Mico8_Instr_0$n145: 39 loads
Net Mico8_Instr_13: 35 loads
Net MicoAddr_2: 34 loads
Net I78/u1_isp8/iels_ie: 31 loads
Net Mico8_Instr_1: 28 loads
Net Mico8_Instr_10$n63: 28 loads
Net Mico8_Instr_11$n65: 28 loads
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
Retiming Report
----------------
Iteration 0 : 11 backward-retiming performed. Estimated slack -4834 -> -4039
Iteration 1 : 12 backward-retiming performed. Estimated slack -4039 -> -3244
Iteration 2 : 2 register-merging performed. Estimated slack -3244 -> -3244
End of Retiming
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
+---------------------+-----------+-----------+------------+------------+
| IO Name | Direction | Levelmode | IO | FIXEDDELAY |
| | | IO_TYPE | Register | |
+---------------------+-----------+-----------+------------+------------+
| Mico_WR | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| CLK_IN | INPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| X2CLK | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| RXD_B | INPUT | LVCMOS33 | IN | |
+---------------------+-----------+-----------+------------+------------+
| RXD_A | INPUT | LVCMOS33 | IN | |
+---------------------+-----------+-----------+------------+------------+
| DIP8_7 | INPUT | LVCMOS33 | IN | |
+---------------------+-----------+-----------+------------+------------+
| DIP8_6 | INPUT | LVCMOS33 | IN | |
+---------------------+-----------+-----------+------------+------------+
| DIP8_5 | INPUT | LVCMOS33 | IN | |
+---------------------+-----------+-----------+------------+------------+
| DIP8_4 | INPUT | LVCMOS33 | IN | |
+---------------------+-----------+-----------+------------+------------+
| DIP8_3 | INPUT | LVCMOS33 | IN | |
+---------------------+-----------+-----------+------------+------------+
| DIP8_2 | INPUT | LVCMOS33 | IN | |
+---------------------+-----------+-----------+------------+------------+
| DIP8_1 | INPUT | LVCMOS33 | IN | |
+---------------------+-----------+-----------+------------+------------+
| DIP8_0 | INPUT | LVCMOS33 | IN | |
+---------------------+-----------+-----------+------------+------------+
| Segm2_6 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm2_5 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm2_4 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm2_3 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm2_2 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm2_1 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm2_0 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm1_6 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm1_5 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm1_4 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm1_3 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm1_2 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm1_1 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| Segm1_0 | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| RC5_PWR | OUTPUT | LVCMOS33 | | |
+---------------------+-----------+-----------+------------+------------+
| LCD_RS | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LCD_D_7 | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LCD_D_6 | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LCD_D_5 | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LCD_D_4 | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LCD_D_3 | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LCD_D_2 | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LCD_D_1 | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LCD_D_0 | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LCD_EN | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| TXD | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| PWM | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LEDs_7 | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LEDs_6 | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LEDs_5 | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| LEDs_4 | OUTPUT | LVCMOS33 | OUT | |
+---------------------+-----------+-----------+------------+------------+
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