automake.log

Lattice 超精简8位软核CPU--Mico8

PAR: Place And Route ispLever_v70_Prod_Build (55).
Command line: C:/Tools/Lattice/ispTOOLS7_0/ispfpga\bin\nt\par -f mico8.p2t mico8_map.ncd
mico8.dir mico8.prf
Preference file: mico8.prf.
Placement level-cost: 5-11.
Routing Iterations: 14

Loading design for application par from file mico8_map.ncd.
Design name: MICO8
NCD version: 3.2
Vendor:      LATTICE
Device:      LFE2-6E
Package:     TQFP144
Speed:       7
Loading device for application par from file 'ep5a32x29.nph' in environment
C:/Tools/Lattice/ispTOOLS7_0/ispfpga.
Package: Version 1.30, Status: FINAL
Speed Hardware Data: version 1.209.1.5


Ignore Preference Error(s):  True
Dumping design to file C:/DOCUME~1/GREGOR~1/LOCALS~1/Temp/neo_6.
Device utilization summary:


   PIO               54/208          25% used
                     54/90           60% bonded

   IOLOGIC           32/208          15% used
   SLICE            359/3024         11% used

   GSR                1/1           100% used
   EBR                1/3            33% used
   PLL                1/2            50% used


Number of Signals: 1122
Number of Connections: 3331

Pin Constraint Summary:
   53 out of 54 pins locked (98% locked).

WARNING - par: Some input signals of PLL instance "I47/PLLDInst_0" may not
          be able to use the dedicated CLKI / CLKFB input pins (possible
          reason: pin locking; the input signal is also a primary /
          secondary clock; unbonded PLL CLKI / CLKFB dedicated pins), and
          this may sacrifice the performance of this PLL instance.  Please
          check the design constraints carefully if necessary.
The following 2 signals are selected to use the primary clock routing resources:
    CLK_IN_c (driver: CLK_IN, clk load #: 1)
    MicoCLK (driver: I47/PLLDInst_0, clk load #: 258)

No signal is selected as DCS clock.

No signal is selected as secondary clock.

Signal nReset_c is selected as Global Set/Reset.
Starting Placer Phase 0.
...........
Finished Placer Phase 0.  REAL time: 7 secs 

Starting Placer Phase 1.
Placer score =  327624
Placer score =  30638165
Placer score =  19274430
Placer score =  17453731
Placer score =  17579609
Placer score =  16888771
Placer score =  18034653
Placer score =  17069914
Placer score =  17608396

Placer score = 17789156.
Finished Placer Phase 1.  REAL time: 19 secs 

Starting Placer Phase 2.
.
Placer score =  17250732
Finished Placer Phase 2.  REAL time: 19 secs 


------------------ Clock Report ------------------

Global Clock Resources:
  CLK_PIN    : 1 out of 8 (12%)
  PLL        : 1 out of 2 (50%)
  DCS        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "CLK_IN_c" from CLK_PIN "14", driver "CLK_IN", clk load = 1
  PRIMARY "MicoCLK" from PLL_CLKOK "PLL_R19C3.CLKOK", driver "I47/PLLDInst_0", clk load = 258

  PRIMARY  : 2 out of 8 (25%)
     DCS   : 0 out of 2 (0%)
  SECONDARY: 0 out of 4 (0%)

Edge Clocks:
  No edge clock selected

--------------- End of Clock Report ---------------


I/O Usage Summary:
   54 out of 208 (25%) PIO sites used.
   54 out of 90 (60%) bonded PIO sites used.
   Number of PIO comps: 54; differential: 0
   Number of Vref pins used: 0

INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The
use of the EBR block asynchronous reset requires that certain timing be met
between the clock and the reset within the memory block. See the device
specific datasheet for additional details.
INFO: Design contains pre-loadable EBR during configuration that has a
requirement:Since the GSR is disabled for the EBR, make sure write enable
and chip enable are inactive during wake-up, so that the pre-loaded
initialization values will not be corrupted during wake-up state.

DSP Utilization Summary:
-------------------------------------
DSP Block #:              1 2 3
# of MULT36X36B                
# of MULT18X18B                
# of MULT18X18MACB             
# of MULT18X18ADDSUBB          
# of MULT18X18ADDSUBSUMB       
# of MULT9X9B                  
# of MULT9X9ADDSUBB            
# of MULT9X9ADDSUBSUMB         

Total placer CPU time: 19 secs 

Dumping design to file mico8.dir/5_11.ncd.

0 connections routed; 3331 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 22 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
3331 successful; 0 unrouted; (1258863) real time: 25 secs 
Dumping design to file mico8.dir/5_11.ncd.
End of iteration 2
3331 successful; 0 unrouted; (1255472) real time: 28 secs 
Dumping design to file mico8.dir/5_11.ncd.
End of iteration 3
3331 successful; 0 unrouted; (1249569) real time: 30 secs 
Dumping design to file mico8.dir/5_11.ncd.
End of iteration 4
3331 successful; 0 unrouted; (1244164) real time: 33 secs 
Dumping design to file mico8.dir/5_11.ncd.
End of iteration 5
3331 successful; 0 unrouted; (1244963) real time: 35 secs 
End of iteration 6
3331 successful; 0 unrouted; (1243512) real time: 38 secs 
Dumping design to file mico8.dir/5_11.ncd.
End of iteration 7
3331 successful; 0 unrouted; (1244311) real time: 42 secs 
End of iteration 8
3331 successful; 0 unrouted; (1240359) real time: 46 secs 
Dumping design to file mico8.dir/5_11.ncd.
End of iteration 9
3331 successful; 0 unrouted; (1243960) real time: 53 secs 
End of iteration 10
3331 successful; 0 unrouted; (1240359) real time: 57 secs 
End of iteration 11
3331 successful; 0 unrouted; (1240784) real time: 1 mins 4 secs 
End of iteration 12
3331 successful; 0 unrouted; (1240359) real time: 1 mins 9 secs 
End of iteration 13
3331 successful; 0 unrouted; (1241158) real time: 1 mins 14 secs 
End of iteration 14
3331 successful; 0 unrouted; (1240271) real time: 1 mins 18 secs 
Dumping design to file mico8.dir/5_11.ncd.
Starting cleanup 
End of cleanup iteration 1
3331 successful; 0 unrouted; (1238183) real time: 1 mins 19 secs 
Dumping design to file mico8.dir/5_11.ncd.
End of cleanup iteration 2
3331 successful; 0 unrouted; (1238183) real time: 1 mins 21 secs 
End of cleanup iteration 3
3331 successful; 0 unrouted; (1238183) real time: 1 mins 23 secs 

Starting timing optimization.
End of timing optimization 1
3331 successful; 0 unrouted; (1230145) real time: 1 mins 25 secs 
Dumping design to file mico8.dir/5_11.ncd.
End of timing optimization 2
3331 successful; 0 unrouted; (1230145) real time: 1 mins 27 secs 
End of timing optimization 3
3331 successful; 0 unrouted; (1230145) real time: 1 mins 29 secs 

Hold time optimization iteration 0:
All hold time violations have been successfully corrected in speed grade M

Dumping design to file mico8.dir/5_11.ncd.
Total CPU time 1 mins 34 secs 
Total REAL time: 1 mins 42 secs 
Completely routed.
End of route.  3331 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.
Exiting par with exit code 0
Exiting multipar with exit code 0
Done: completed successfully.

Starting: 'C:\Tools\Lattice\ispTOOLS7_0\ispfpga\bin\nt\trce.exe  -f "mico8.pt" -o mico8.twr mico8.ncd mico8.prf'

trce:  version ispLever_v70_Prod_Build (55)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
     Copyright (c) 1995 AT&T Corp.   All rights reserved.
     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
     Copyright (c) 2001 Agere Systems   All rights reserved.
     Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights
     reserved.

Loading design for application trce.exe from file mico8.ncd.
Design name: MICO8
NCD version: 3.2
Vendor:      LATTICE
Device:      LFE2-6E
Package:     TQFP144
Speed:       7
Loading device for application trce.exe from file 'ep5a32x29.nph' in
environment C:/Tools/Lattice/ispTOOLS7_0/ispfpga.
Package: Version 1.30, Status: FINAL
Speed Hardware Data: version 1.209.1.5
--------------------------------------------------------------------------------
Lattice TRACE Report, Version ispLever_v70_SP2_Build (24)
Fri Mar 14 11:45:14 2008

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce.exe -v 1 -o mico8.twr mico8.ncd mico8.prf 
Design file:     mico8.ncd
Preference file: mico8.prf
Device,speed:    LFE2-6E,7
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------


Derating parameters
-------------------
Temperature:   25 C
Voltage:    1.200 V  (Preference `VCC_DERATE` is ignored)



Timing summary:
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 9704 paths, 233 nets, and 3034 connections (91.1% coverage)

--------------------------------------------------------------------------------

Total time: 6 secs 
Done: completed successfully.

Starting: 'C:\Tools\Lattice\ispTOOLS7_0\ispfpga\bin\nt\htmlrpt.exe  -f "mico8.rsp"'

Done: completed successfully.