automake.log

Lattice 超精简8位软核CPU--Mico8

ispLEVER Auto-Make Log File
---------------------------

Updating: Report Summary - HTML

Starting: 'C:\Tools\Lattice\ispTOOLS7_0\ispfpga\bin\nt\map.exe  -a LatticeECP2 -p LFE2-6E -t TQFP144 -s 7 "mico8.ngd" -o "mico8_map.ncd" -mp "mico8.mrp" "mico8.lpf" -c 0 -m -retime EFFORT=5:DETOUR=5 -tdm -split_node -td_pack'

map:  version ispLever_v70_Prod_Build (55)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
     Copyright (c) 1995 AT&T Corp.   All rights reserved.
     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
     Copyright (c) 2001 Agere Systems   All rights reserved.
     Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights
     reserved.
   Process the file: mico8.ngd
   Picdevice="LFE2-6E"
   Pictype="TQFP144"
   Picspeed=7
   Remove unused logic
   Produce over sized NCDs.
Part used: LFE2-6ETQFP144, Speed used: 7.
Loading device for application map from file 'ep5a32x29.nph' in environment
     C:/Tools/Lattice/ispTOOLS7_0/ispfpga.
Package: Version 1.30, Status: FINAL

Running general design DRC...
WARNING - map: logical net 'I78/u1_isp8/u1_isp8_alu/Overflow' has no driver
Removing unused logic...
Optimizing...
Absorbing 144 CCU2 constant inputs...

Retiming Report
----------------
Iteration 0 : 11 backward-retiming performed. Estimated slack -4834 -> -4039
Iteration 1 : 12 backward-retiming performed. Estimated slack -4039 -> -3244
Iteration 2 : 2 register-merging performed. Estimated slack -3244 -> -3244
End of Retiming

-345
-27600
-27600
-345
-27600
-27600
-345
-27600
-27600
-345
-27600
-27600
-345
-27600
-27600
-345
-27600
-27600
-345
-27600
-27600
-345
-27600
-27600
-345
-27600
-27600
-345
-27600
-27600





Design Summary:
   Number of registers:    345
      PFU registers:    313
      PIO registers:    32
   Number of SLICEs:           359 out of  3024 (12%)
      SLICEs(logic/ROM):       314 out of  2457 (13%)
      SLICEs(logic/ROM/RAM):    45 out of   567 (8%)
          As RAM:           45 out of   567 (8%)
          As Logic/ROM:      0 out of   567 (0%)
   Number of logic LUT4s:     484
   Number of distributed RAM:  45 (90 LUT4s)
   Number of ripple logic:     47 (94 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:     668
   Number of external PIOs: 54 out of 90 (60%)
   Number of PIO IDDR/ODDR:     0
   Number of PIO FIXEDDELAY:    0
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of 3-state buffers:   0
   Number of PLLs:  1 out of 2 (50%)
   Number of DLLs:  0 out of 2 (0%)
   Number of block RAMs:  1 out of 3 (33%)
   Number of CLKDIVs:  0 out of 2 (0%)
   Number of GSRs:  1 out of 1 (100%)
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.

DSP Component Details --
------------------------

   Number Of Mapped DSP Components:
   --------------------------------
   MULT36X36B          0
   MULT18X18B          0
   MULT18X18MACB       0
   MULT18X18ADDSUBB    0
   MULT18X18ADDSUBSUMB 0
   MULT9X9B            0
   MULT9X9ADDSUBB      0
   MULT9X9ADDSUBSUMB   0
   --------------------------------
   Number of clocks:  1
     Net MicoCLK: 256 loads, 256 rising, 0 falling (Driver: I47/PLLDInst_0 )
   Number of Clock Enables:  34
     Net I72_txdata8_5_i: 2 loads, 0 LSLICEs
     Net N_41_i: 1 loads, 0 LSLICEs
     Net I78_u1_isp8_u1_isp8_flow_cntl_data_cyc_int: 7 loads, 5 LSLICEs
     Net I65/un1_ser_out_1_i_0: 3 loads, 3 LSLICEs
     Net I65/dserdata_0_sqmuxa: 4 loads, 4 LSLICEs
     Net I70/duty_0_sqmuxa: 4 loads, 4 LSLICEs
     Net I69_LEDs_Out_0_sqmuxa: 8 loads, 0 LSLICEs
     Net I72/StartSending_1_sqmuxa_i: 1 loads, 1 LSLICEs
     Net TxState_14: 2 loads, 1 LSLICEs
     Net I72/txdata8: 4 loads, 4 LSLICEs
     Net I72/N_86_i: 4 loads, 4 LSLICEs
     Net I71_LCD_Enable_1_sqmuxa: 2 loads, 0 LSLICEs
     Net I71_LCD_Data_0_sqmuxa: 8 loads, 0 LSLICEs
     Net I74/Leds_out_0_sqmuxa: 4 loads, 4 LSLICEs
     Net I75/N_274_i: 3 loads, 3 LSLICEs
     Net I75/un1_per2_reg12_i_s_0: 4 loads, 4 LSLICEs
     Net I75/un1_per1_reg12_i_s_0: 4 loads, 4 LSLICEs
     Net I75/un1_per0_reg12_i_s_0: 4 loads, 4 LSLICEs
     Net I75/un1_Mico8_INT_1_sqmuxa_1_0_i: 1 loads, 1 LSLICEs
     Net I75/INT_REG_0_sqmuxa_i_s: 3 loads, 3 LSLICEs
     Net I76/Data_Out_0_sqmuxa: 4 loads, 4 LSLICEs
     Net I77/buffer_empty_1_sqmuxa_i: 1 loads, 1 LSLICEs
     Net I77/un1_timecounter_pulse_0_a2_0: 7 loads, 7 LSLICEs
     Net I77/N_139_i: 1 loads, 1 LSLICEs
     Net I77/un17_timecounter_pulse_0_a2_0: 4 loads, 4 LSLICEs
     Net I79/un1_timecounter_pulse_0_a2: 7 loads, 7 LSLICEs
     Net I79/buffer_empty_1_sqmuxa_i: 1 loads, 1 LSLICEs
     Net I79/N_139_i: 1 loads, 1 LSLICEs
     Net I79/un17_timecounter_pulse_0_a2: 4 loads, 4 LSLICEs
     Net I78/u1_isp8/addr_cyc: 9 loads, 9 LSLICEs
     Net I78/u1_isp8/u1_isp8_flow_cntl/N_285_i: 1 loads, 1 LSLICEs
     Net I78/u1_isp8/u1_isp8_flow_cntl/N_20: 1 loads, 1 LSLICEs
     Net I78/u1_isp8/u1_isp8_flow_cntl/N_287_i: 1 loads, 1 LSLICEs
     Net I78/u1_isp8/u1_isp8_flow_cntl/N_286_i: 7 loads, 7 LSLICEs
   Number of LSRs:  9
     Net un1_reset_1: 1 loads, 1 LSLICEs
     Net un1_reset: 1 loads, 1 LSLICEs
     Net I78/u1_isp8/u1_isp8_flow_cntl/N_22: 3 loads, 3 LSLICEs
     Net I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/dec_wre7: 2 loads, 2 LSLICEs
     Net I78/u1_isp8/GEN_REG_32_u1_isp8_rfmem/dec_wre3: 2 loads, 2 LSLICEs
     Net I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/dec_wre7: 2 loads, 2 LSLICEs
     Net I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/dec_wre3: 2 loads, 2 LSLICEs
     Net I78/U2_scratchpad/dec_wre7: 2 loads, 2 LSLICEs
     Net I78/U2_scratchpad/dec_wre3: 2 loads, 2 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net VCC: 74 loads
     Net MicoAddr_1: 46 loads
     Net MicoAddr_0: 45 loads
     Net Mico8_Instr_0$n145: 39 loads
     Net Mico8_Instr_13: 35 loads
     Net MicoAddr_2: 34 loads
     Net I78/u1_isp8/iels_ie: 31 loads
     Net Mico8_Instr_1: 28 loads
     Net Mico8_Instr_10$n63: 28 loads
     Net Mico8_Instr_11$n65: 28 loads


INFO: Design contains EBR with ASYNC Reset Mode that has a limitation:
The use of the EBR block asynchronous reset requires that certain timing
be met between the clock and the reset within the memory block. 
See the device specific data sheet for additional details.


INFO: Design contains pre-loadable EBR during configuration that has a requirement:
Since the GSR is disabled for the EBR, make sure write enable and chip
enable are inactive during wake-up, so that the pre-loaded initialization
values will not be corrupted during wake-up state.
   Number of warnings:  0
   Number of errors:    0

Total CPU Time: 2 secs  
Total REAL Time: 3 secs  
Peak Memory Usage: 43 MB

Dumping design to file mico8_map.ncd.
Done: completed successfully.

Starting: 'C:\Tools\Lattice\ispTOOLS7_0\ispcpld\bin\checkpoint.exe -m -f "mico8.cmm" -f "mico8.cm2" -arch LatticeECP2 "mico8_map.ncd"'


---- Checkpoint Tool Log File ----

==== Trace Standard Out ====
trce:  version ispLever_v70_Prod_Build (55)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
     Copyright (c) 1995 AT&T Corp.   All rights reserved.
     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
     Copyright (c) 2001 Agere Systems   All rights reserved.
     Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights
     reserved.

Loading design for application trce from file mico8_map.ncd.
Design name: MICO8
NCD version: 3.2
Vendor:      LATTICE
Device:      LFE2-6E
Package:     TQFP144
Speed:       7
Loading device for application trce from file 'ep5a32x29.nph' in
environment C:/Tools/Lattice/ispTOOLS7_0/ispfpga.
Package: Version 1.30, Status: FINAL
Speed Hardware Data: version 1.209.1.5
--------------------------------------------------------------------------------
Lattice TRACE Report, Version ispLever_v70_SP2_Build (24)
Fri Mar 14 11:43:24 2008

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -o checkpnt.twr mico8_map.ncd mico8.prf 
Design file:     mico8_map.ncd
Preference file: mico8.prf
Device,speed:    LFE2-6E,7
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------


Derating parameters
-------------------
Temperature:   25 C
Voltage:    1.200 V  (Preference `VCC_DERATE` is ignored)



Timing summary:
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 9704 paths, 233 nets, and 3001 connections (90.1% coverage)

--------------------------------------------------------------------------------

Total time: 6 secs 
==== End of Trace Standard Out ====

*********************************
Map checkpoint failed.
Design's logic delay (54 percent of total delay) 
exceeds the 50 percent limit set in the map checkpoint options
*********************************
 Process Continuing ...

Done: completed successfully.

Starting: 'C:\Tools\Lattice\ispTOOLS7_0\ispcpld\bin\multipar.exe -p mico8.p2t -f "mico8.p3t" "mico8_map.ncd" "mico8.ncd"'

---- Multipar Tool ----

Removing old design directory at request of -rem command line option to
this program.
Running par. Please wait . . .

Lattice Place and Route Report for Design "mico8_map.ncd"
Fri Mar 14 11:43:25 2008