isp8_core.vhd

Lattice 超精简8位软核CPU--Mico8

        generic map(PROM_AW => PROM_AW)
        port map(instr      => instr,
                 imi_instr  => imi_instr,
                 sub        => sub,
                 subc       => subc,
                 add        => add,
                 addc       => addc,
                 mov        => mov,
                 andr       => andr,
                 orr        => orr,
                 xorr       => xorr,
                 cmp        => cmp,
                 test       => test,
                 ror1       => ror1,
                 rorc       => rorc,
                 rol1       => rol1,
                 rolc       => rolc,
                 clrc       => clrc,
                 setc       => setc,
                 clrz       => clrz,
                 setz       => setz,
                 clri       => clri,
                 seti       => seti,
                 bz         => bz,
                 bnz        => bnz,
                 bc         => bc,
                 bnc        => bnc,
                 b          => b,
                 callz      => callz,
                 callnz     => callnz,
                 callc      => callc,
                 callnc     => callnc,
                 call       => call,
                 ret        => ret,
                 iret       => iret,
                 export     => export,
                 exporti    => exporti,
                 import     => import,
                 importi    => importi,
                 ssp        => ssp,
                 lsp        => lsp,
                 sspi       => sspi,
                 lspi       => lspi,
                 addr_rb    => addr_rb,
                 addr_rd    => addr_rd,
                 imi_data   => imi_data,
                 addr_jmp   => addr_jmp,
                 update_c   => update_c,
                 update_z   => update_z);


-- Instantiate Arithmetic/logic unit.
    u1_isp8_alu : isp8_alu
       generic map (
          FAMILY_NAME      => FAMILY_NAME)
       port map(instr      => instr,
                dout_rd    => dout_rd,
                dout_rb    => dout_rb,
                imi_data   => imi_data,
                imi_instr  => imi_instr,
                carry_flag => carry_flag,
                sub        => sub,
                subc       => subc,
                addc       => addc,
                cmp        => cmp,
                dout_alu   => dout_alu,
                cout_alu   => cout_alu);


-- Instantiate flags/instruction read controller.
    u1_isp8_flow_cntl: isp8_flow_cntl

       generic map(PROM_AW      => PROM_AW,
                   FAMILY_NAME  => FAMILY_NAME,
                   PGM_STACK_AW => PGM_STACK_AW,
                   PGM_STACK_AD => PGM_STACK_AD)
       port map(clk                 => clk,
                rst_n               => rst_n,
                setc                => setc,
                clrc                => clrc,
                setz                => setz,
                clrz                => clrz,
                seti                => seti,
                clri                => clri,
                addr_jmp            => addr_jmp,
                update_c            => update_c,
                update_z            => update_z,
                cout_alu            => cout_alu,
                dout_alu            => dout_alu,
                bz                  => bz,
                bnz                 => bnz,
                bc                  => bc,
                bnc                 => bnc,
                b                   => b,
                callz               => callz,
                callnz              => callnz,
                callc               => callc,
                callnc              => callnc,
                call                => call,
                ret                 => ret,
                iret                => iret,
                intr                => intr,
                lsp                 => lsp,
                lspi                => lspi,
                ssp                 => ssp,
                sspi                => sspi,
                import              => import,
                importi             => importi,
                export              => export,
                exporti             => exporti,
                ready               => ext_mem_ready,
                addr_cyc            => addr_cyc,
                ext_addr_cyc        => ext_addr_cyc_int,
                data_cyc            => data_cyc,
                prom_addr           => prom_addr,
                carry_flag          => carry_flag,
                intr_ack            => intr_ack);

    ext_addr_cyc <= ext_addr_cyc_int;
    
-- Instantiate IO controller.
    u1_isp8_io_cntl: isp8_io_cntl
       generic map(
          PORT_AW               => PORT_AW)
       port map(
          clk                   => clk,
          rst_n                 => rst_n,
          import                => import,
          importi               => importi,
          export                => export,
          exporti               => exporti,
          ssp                   => ssp,
          sspi                  => sspi,
          lsp                   => lsp,
          lspi                  => lspi,
          addr_cyc              => addr_cyc,
          addr_rb               => addr_rb,
          dout_rd               => dout_rd,
          dout_rb               => dout_rb,
          ext_addr              => local_ext_addr,
          ext_dout              => ext_dout,
          ext_mem_wr            => ext_mem_wr,
          ext_mem_rd            => ext_mem_rd,
          ext_addr_cyc          => ext_addr_cyc_int,
          ext_io_wr             => ext_io_wr,
          ext_io_rd             => ext_io_rd);

-- Instantiate EBR PROM for Instruction Memory.
--    u1_isp8_prom : pmi_rom
--       generic map (
--          pmi_addr_depth       => PROM_AD,
--          pmi_addr_width       => PROM_AW,
--          pmi_data_width       => 18,
--          pmi_regmode          => "noreg",
--          pmi_gsr              => "disable",
--          pmi_resetmode        => "async",
--          pmi_init_file        => PROM_FILE,
--          pmi_init_file_format => "hex",
--          pmi_family           => FAMILY_NAME,
--          module_type          => "pmi_rom")
--        port map(Address       => prom_addr((PROM_AW - 1) downto 0),
--                 OutClock      => clk,
--                 OutClockEn    => data_cyc,
--                 Reset         => lo_val,
--                 Q             => instr);


    GEN_PAGE_PTR1: if ((EXT_AW > 8) and (EXT_AW <= 24)) = true generate
       process(clk, rst_n, page_ptr1)
       begin
          if (rst_n = '0') then
             page_ptr1 <= (others => '0');
          elsif rising_edge(clk) then
             page_ptr1 <= page_ptr1;
             if (addr_rd = REG14) and (wren_rd = '1') then
                page_ptr1 <= din_rd;
             end if;
          end if;
       end process;
    end generate;

    GEN_PAGE_PTR2: if ((EXT_AW > 16) and (EXT_AW <= 24)) = true generate
       process(clk, rst_n)
       begin
          if (rst_n = '0') then
             page_ptr2 <= (others => '0');
          elsif rising_edge(clk) then
             page_ptr2 <= page_ptr2;
             if (addr_rd = REG15) and (wren_rd = '1') then
                page_ptr2 <= din_rd;
             end if;
          end if;
       end process;
    end generate;

--Instantiate dual port Distributed RAM for Register file.
    GEN_REG_16: if REGISTERS_16 = true generate

        u1_isp8_rfmem : pmi_distributed_dpram
           generic map (
              pmi_addr_depth       => 16,
              pmi_addr_width       => 4,
              pmi_data_width       => 8,
              pmi_regmode          => "noreg",
              pmi_init_file        => "none",
              pmi_init_file_format => "binary",
              pmi_family           => FAMILY_NAME,
              module_type          => "pmi_distributed_dpram")
            port map(WrAddress     => addr_rd(3 downto 0),
                     Data          => din_rd,
                     WrClock       => clk,
                     WE            => wren_rd,
                     WrClockEn     => hi_val,
                     RdAddress     => addr_rb(3 downto 0),
                     RdClock       => clk,
                     RdClockEn     => hi_val,
                     Reset         => lo_val,
                     Q             => dout_rb);

        u2_isp8_rfmem : pmi_distributed_dpram
           generic map (
              pmi_addr_depth       => 16,
              pmi_addr_width       => 4,
              pmi_data_width       => 8,
              pmi_regmode          => "noreg",
              pmi_init_file        => "none",
              pmi_init_file_format => "binary",
              pmi_family           => FAMILY_NAME,
              module_type          => "pmi_distributed_dpram")
            port map(WrAddress     => addr_rd(3 downto 0),
                     Data          => din_rd,
                     WrClock       => clk,
                     WE            => wren_rd,
                     WrClockEn     => hi_val,
                     RdAddress     => addr_rd(3 downto 0),
                     RdClock       => clk,
                     RdClockEn     => hi_val,
                     Reset         => lo_val,
                     Q             => dout_rd);

    end generate GEN_REG_16;

    GEN_REG_32: if REGISTERS_16 = false generate

       u1_isp8_rfmem : pmi_distributed_dpram
          generic map (
             pmi_addr_depth       => 32,
             pmi_addr_width       => 5,
             pmi_data_width       => 8,
             pmi_regmode          => "noreg",
             pmi_init_file        => "none",
             pmi_init_file_format => "binary",
             pmi_family           => FAMILY_NAME,
             module_type          => "pmi_distributed_dpram")
          port map(
             WrAddress            => addr_rd,
             Data                 => din_rd,
             WrClock              => clk,
             WE                   => wren_rd,
             WrClockEn            => hi_val,
             RdAddress            => addr_rb,
             RdClock              => clk,
             RdClockEn            => hi_val,
             Reset                => lo_val,
             Q                    => dout_rb);

        u2_isp8_rfmem : pmi_distributed_dpram
           generic map (
              pmi_addr_depth       => 32,
              pmi_addr_width       => 5,
              pmi_data_width       => 8,
              pmi_regmode          => "noreg",
              pmi_init_file        => "none",
              pmi_init_file_format => "binary",
              pmi_family           => FAMILY_NAME,
              module_type          => "pmi_distributed_dpram")
            port map(WrAddress     => addr_rd,
                     Data          => din_rd,
                     WrClock       => clk,
                     WE            => wren_rd,
                     WrClockEn     => hi_val,
                     RdAddress     => addr_rd,
                     RdClock       => clk,
                     RdClockEn     => hi_val,
                     Reset         => lo_val,
                     Q             => dout_rd);

    end generate GEN_REG_32;



-----------------------------------------------------------------------
-- Registered data and write enable for register file memory
    process(clk, rst_n)
    begin
       if (rst_n = '0') then
          wren_alu_rd <= '0';
          wren_il_rd  <= '0';
       elsif rising_edge(clk) then
          wren_alu_rd <= (add OR addc OR sub OR subc OR mov OR andr OR 
                          orr OR xorr OR ror1 OR rorc OR rol1 OR rolc);
          wren_il_rd  <= (import OR importi OR lsp OR lspi);
       end if;
    end process;

    process(clk, rst_n)
    begin
       if (rst_n = '0') then
          din_rd1 <= "00000000";
       elsif rising_edge(clk) then
          din_rd1 <= dout_alu;
       end if;
    end process;

    process(import, importi, lsp, lspi, ext_mem_din, ext_io_din, din_rd1)
    begin
       if ((lspi = '1') or (lsp = '1')) then
          din_rd <= ext_mem_din;
       elsif ((import = '1') OR (importi = '1')) then
          din_rd <= ext_io_din;
       else
          din_rd <= din_rd1;
       end if;
    end process;


    wren_rd <= ((wren_alu_rd OR wren_il_rd) AND data_cyc);


end behave;

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