📄 isp8_core.vhd
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------------------------------------------------------------------------------
--
-- Name: isp8_core.vhd
--
-- Description: Top level for Mico8 core
--
-- $Revision: 1.3 $
--
------------------------------------------------------------------------------
-- Permission:
--
-- Lattice Semiconductor grants permission to use this code for use
-- in synthesis for any Lattice programmable logic product. Other
-- use of this code, including the selling or duplication of any
-- portion is strictly prohibited.
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice Semiconductor provides no warranty
-- regarding the use or functionality of this code.
------------------------------------------------------------------------------
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97124
-- U.S.A
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: techsupport@latticesemi.com
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity isp8_core is
generic(FAMILY_NAME : string := "ECP2";
-- PROM_FILE : string := "prom_init.hex";
PORT_AW : natural := 8;
EXT_AW : natural := 24;
PROM_AW : natural := 12;
PROM_AD : natural := 4096;
REGISTERS_16 : boolean := FALSE;
PGM_STACK_AW : natural := 4;
PGM_STACK_AD : natural := 16);
port(clk : in std_logic;
rst_n : in std_logic;
ext_mem_din : in std_logic_vector(7 downto 0);
ext_mem_ready : in std_logic;
ext_io_din : in std_logic_vector(7 downto 0);
intr : in std_logic;
ext_addr : out std_logic_vector((EXT_AW - 1) downto 0);
ext_addr_cyc : out std_logic;
ext_dout : out std_logic_vector(7 downto 0);
ext_mem_wr : out std_logic;
ext_mem_rd : out std_logic;
ext_io_wr : out std_logic;
ext_io_rd : out std_logic;
intr_ack : out std_logic;
-- PROM external
prom_addr : out std_logic_vector((PROM_AW - 1) downto 0);
-- clk
data_cyc : inout std_logic;
instr : in std_logic_vector(17 downto 0);
Zero : out std_logic);
end isp8_core;
architecture behave of isp8_core is
constant REG14 : std_logic_vector(4 downto 0) := "01110";
constant REG15 : std_logic_vector(4 downto 0) := "01111";
component isp8_idec
generic(PROM_AW : natural);
port(instr : in std_logic_vector(17 downto 0);
imi_instr : out std_logic;
sub : out std_logic;
subc : out std_logic;
add : out std_logic;
addc : out std_logic;
mov : out std_logic;
andr : out std_logic;
orr : out std_logic;
xorr : out std_logic;
cmp : out std_logic;
test : out std_logic;
ror1 : out std_logic;
rorc : out std_logic;
rol1 : out std_logic;
rolc : out std_logic;
clrc : out std_logic;
setc : out std_logic;
clrz : out std_logic;
setz : out std_logic;
clri : out std_logic;
seti : out std_logic;
bz : out std_logic;
bnz : out std_logic;
bc : out std_logic;
bnc : out std_logic;
b : out std_logic;
callz : out std_logic;
callnz : out std_logic;
callc : out std_logic;
callnc : out std_logic;
call : out std_logic;
ret : out std_logic;
iret : out std_logic;
export : out std_logic;
exporti : out std_logic;
import : out std_logic;
importi : out std_logic;
ssp : out std_logic;
lsp : out std_logic;
sspi : out std_logic;
lspi : out std_logic;
addr_rb : out std_logic_vector(4 downto 0);
addr_rd : out std_logic_vector(4 downto 0);
imi_data : out std_logic_vector(7 downto 0);
addr_jmp : out std_logic_vector((PROM_AW - 1) downto 0);
update_c : out std_logic;
update_z : out std_logic);
end component;
component isp8_alu
generic (
FAMILY_NAME : string);
port(instr : in std_logic_vector(17 downto 0);
dout_rd : in std_logic_vector(7 downto 0);
dout_rb : in std_logic_vector(7 downto 0);
imi_data : in std_logic_vector(7 downto 0);
imi_instr : in std_logic;
carry_flag : in std_logic;
sub : in std_logic;
subc : in std_logic;
addc : in std_logic;
cmp : in std_logic;
dout_alu : out std_logic_vector(7 downto 0);
cout_alu : out std_logic);
end component;
component isp8_flow_cntl
generic(PROM_AW: natural;
FAMILY_NAME : string;
PGM_STACK_AW : natural;
PGM_STACK_AD : natural);
port(clk : in std_logic;
rst_n : in std_logic;
setc : in std_logic;
clrc : in std_logic;
setz : in std_logic;
clrz : in std_logic;
seti : in std_logic;
clri : in std_logic;
addr_jmp : in std_logic_vector((PROM_AW - 1) downto 0);
update_c : in std_logic;
update_z : in std_logic;
cout_alu : in std_logic;
dout_alu : in std_logic_vector(7 downto 0);
bz : in std_logic;
bnz : in std_logic;
bc : in std_logic;
bnc : in std_logic;
b : in std_logic;
callz : in std_logic;
callnz : in std_logic;
callc : in std_logic;
callnc : in std_logic;
call : in std_logic;
ret : in std_logic;
iret : in std_logic;
intr : in std_logic;
lsp : in std_logic;
lspi : in std_logic;
ssp : in std_logic;
sspi : in std_logic;
import : in std_logic;
importi : in std_logic;
export : in std_logic;
exporti : in std_logic;
ready : in std_logic;
addr_cyc : out std_logic;
ext_addr_cyc : out std_logic;
data_cyc : out std_logic;
prom_addr : out std_logic_vector((PROM_AW - 1) downto 0);
carry_flag : out std_logic;
intr_ack : out std_logic);
end component;
component isp8_io_cntl
generic(PORT_AW: natural);
port(clk : in std_logic;
rst_n : in std_logic;
import : in std_logic;
importi : in std_logic;
export : in std_logic;
exporti : in std_logic;
ssp : in std_logic;
sspi : in std_logic;
lsp : in std_logic;
lspi : in std_logic;
addr_cyc : in std_logic;
ext_addr_cyc : in std_logic;
addr_rb : in std_logic_vector(4 downto 0);
dout_rd : in std_logic_vector(7 downto 0);
dout_rb : in std_logic_vector(7 downto 0);
ext_addr : out std_logic_vector((PORT_AW- 1) downto 0);
ext_dout : out std_logic_vector(7 downto 0);
ext_mem_wr : out std_logic;
ext_mem_rd : out std_logic;
ext_io_wr : out std_logic;
ext_io_rd : out std_logic);
end component;
-- component pmi_rom
-- generic (
-- pmi_addr_depth : integer;
-- pmi_addr_width : integer;
-- pmi_data_width : integer;
-- pmi_regmode : string;
-- pmi_gsr : string;
-- pmi_resetmode : string;
-- pmi_init_file : string;
-- pmi_init_file_format : string;
-- pmi_family : string;
-- module_type : string);
-- port (
-- Address : in std_logic_vector((PROM_AW- 1) downto 0);
-- OutClock : in std_logic;
-- OutClockEn : in std_logic;
-- Reset : in std_logic;
-- Q : out std_logic_vector(17 downto 0));
-- end component;
component pmi_distributed_dpram
generic (
pmi_addr_depth : integer;
pmi_addr_width : integer;
pmi_data_width : integer;
pmi_regmode : string;
pmi_init_file : string;
pmi_init_file_format : string;
pmi_family : string;
module_type : string);
port (
WrAddress : in std_logic_vector(pmi_addr_width-1 downto 0);
Data : in std_logic_vector(pmi_data_width-1 downto 0);
WrClock : in std_logic;
WE : in std_logic;
WrClockEn : in std_logic;
RdAddress : in std_logic_vector(pmi_addr_width-1 downto 0);
RdClock : in std_logic;
RdClockEn : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector(pmi_data_width-1 downto 0));
end component;
signal hi_val, lo_val : std_logic;
-- signal instr : std_logic_vector(17 downto 0);
signal imi_instr, sub, subc, add, addc, mov : std_logic;
signal andr, orr, xorr, cmp, test, ror1, rorc : std_logic;
signal rol1, rolc, clrc, setc, clrz, setz : std_logic;
signal clri, seti, bz, bnz, bc, bnc, b : std_logic;
signal callz, callnz, callc, callnc, call : std_logic;
signal ret, iret, export, import, exporti, importi : std_logic;
signal ssp, lsp, sspi, lspi : std_logic;
signal addr_rb : std_logic_vector(4 downto 0);
signal addr_rd : std_logic_vector(4 downto 0);
signal imi_data : std_logic_vector(7 downto 0);
signal addr_jmp : std_logic_vector((PROM_AW - 1) downto 0);
signal update_c,update_z : std_logic;
signal dout_rd : std_logic_vector(7 downto 0);
signal dout_rb : std_logic_vector(7 downto 0);
signal carry_flag : std_logic;
signal dout_alu : std_logic_vector(7 downto 0);
signal cout_alu : std_logic;
signal addr_cyc : std_logic;
signal ext_addr_cyc_int : std_logic;
-- signal data_cyc : std_logic;
-- signal prom_addr : std_logic_vector((PROM_AW - 1) downto 0);
signal wren_alu_rd : std_logic;
signal wren_il_rd : std_logic;
signal din_rd, din_rd1 : std_logic_vector(7 downto 0);
signal wren_rd : std_logic;
signal page_ptr1 : std_logic_vector(7 downto 0);
signal page_ptr2 : std_logic_vector(7 downto 0);
signal local_ext_addr : std_logic_vector((PORT_AW- 1) downto 0);
attribute syn_black_box : boolean;
--attribute syn_black_box of pmi_rom: component is true;
attribute syn_black_box of pmi_distributed_dpram: component is true;
begin
hi_val <= '1';
lo_val <= '0';
zero <= '0';
GEN_ADDR_0: if (EXT_AW <= 8) = true generate
ext_addr <= local_ext_addr;
end generate;
GEN_ADDR_1: if ((EXT_AW > 8) and (EXT_AW < 16)) = true generate
ext_addr <= page_ptr1((EXT_AW mod 8)-1 downto 0) & local_ext_addr;
end generate;
GEN_ADDR_1p: if (EXT_AW = 16) = true generate
ext_addr <= page_ptr1 & local_ext_addr;
end generate;
GEN_ADDR_2: if ((EXT_AW > 16) and (EXT_AW< 24)) = true generate
ext_addr <= page_ptr2((EXT_AW mod 8)-1 downto 0) & page_ptr1 & local_ext_addr;
end generate;
GEN_ADDR_2p: if (EXT_AW = 24) = true generate
ext_addr <= page_ptr2 & page_ptr1 & local_ext_addr;
end generate;
-- Instantiate Instruction Decoder.
u1_isp8_idec : isp8_idec
-- NOTE: Synplicity will not pass generics through instantiations, edit lower block to match
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