my_pll.srp

来自「Lattice 超精简8位软核CPU--Mico8」· SRP 代码 · 共 27 行

SCUBA, Version ispLever_v70_Prod_Build (55)
Mon Mar 10 15:41:50 2008

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Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\Tools\Lattice\ispTOOLS7_0\ispfpga\bin\nt\scuba.exe -w -n My_pll -lang vhdl -synth synplify -arch ep5a00 -type pll -fin 25 -phase_cntl STATIC -fclkop 100 -fclkop_tol 1.0 -delay_cntl STATIC -fdel 0 -noclkos -fclkok 50 -fclkok_tol 10.0 -use_rst -e 
    Circuit name     : My_pll
    Module type      : pll
    Module Version   : 3.7
    Ports            : 
	Inputs       : CLK, RESET
	Outputs      : CLKOP, CLKOK, LOCK
    I/O buffer       : not inserted
    EDIF output      : suppressed
    VHDL output      : My_pll.vhd
    VHDL template    : My_pll_tmpl.vhd
    VHDL purpose     : for synthesis and simulation
    Bus notation     : not used
    Report output    : My_pll.srp
    Element Usage    :
        EHXPLLD : 1
    Estimated Resource Usage: