my_pll.vhd

Lattice 超精简8位软核CPU--Mico8

-- VHDL netlist generated by SCUBA ispLever_v70_SP2_Build (24)
-- Module  Version: 3.7
--C:\Tools\Lattice\ispTOOLS7_0\ispfpga\bin\nt\scuba.exe -w -n My_pll -lang vhdl -synth synplify -arch ep5a00 -type pll -fin 25 -phase_cntl STATIC -fclkop 100 -fclkop_tol 1.0 -delay_cntl STATIC -fdel 0 -noclkos -fclkok 50 -fclkok_tol 10.0 -use_rst -e 

-- Mon Mar 10 15:41:50 2008

library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library ecp2;
use ecp2.components.all;
-- synopsys translate_on

entity My_pll is
    port (
        CLK: in std_logic; 
        RESET: in std_logic; 
        CLKOP: out std_logic; 
        CLKOK: out std_logic; 
        LOCK: out std_logic);
 attribute dont_touch : string;
 attribute dont_touch of My_pll : entity is "true";
end My_pll;

architecture Structure of My_pll is

    -- internal signal declarations
    signal CLKOP_t: std_logic;
    signal CLKFB_t: std_logic;
    signal scuba_vlo: std_logic;
    signal CLK_t: std_logic;

    -- local component declarations
    component VLO
        port (Z: out std_logic);
    end component;
    component EHXPLLD
    -- synopsys translate_off
        generic (CLKOK_BYPASS : in String; CLKOS_BYPASS : in String; 
                CLKOP_BYPASS : in String; DUTY : in Integer; 
                PHASEADJ : in String; PHASE_CNTL : in String; 
                DELAY_CNTL : in String; CLKOK_DIV : in Integer; 
                FDEL : in Integer; CLKFB_DIV : in Integer; 
                CLKOP_DIV : in Integer; CLKI_DIV : in Integer);
    -- synopsys translate_on
        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
            RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic; 
            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
            DFPAI0: in std_logic; DDAMODE: in std_logic; DDAIZR: in std_logic; 
            DDAILAG: in std_logic; DDAIDEL0: in std_logic; DDAIDEL1: in std_logic; 
            DDAIDEL2: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; 
            CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic);
    end component;
    attribute CLKOK_BYPASS : string; 
    attribute FREQUENCY_PIN_CLKOK : string; 
    attribute CLKOK_DIV : string; 
    attribute CLKOS_BYPASS : string; 
    attribute FREQUENCY_PIN_CLKOP : string; 
    attribute CLKOP_BYPASS : string; 
    attribute DELAY_CNTL : string; 
    attribute PHASE_CNTL : string; 
    attribute FDEL : string; 
    attribute DUTY : string; 
    attribute PHASEADJ : string; 
    attribute FREQUENCY_PIN_CLKI : string; 
    attribute CLKOP_DIV : string; 
    attribute CLKFB_DIV : string; 
    attribute CLKI_DIV : string; 
    attribute FIN : string; 
    attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED";
    attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000";
    attribute CLKOK_DIV of PLLDInst_0 : label is "2";
    attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED";
    attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "100.000000";
    attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED";
    attribute DELAY_CNTL of PLLDInst_0 : label is "STATIC";
    attribute PHASE_CNTL of PLLDInst_0 : label is "STATIC";
    attribute FDEL of PLLDInst_0 : label is "0";
    attribute DUTY of PLLDInst_0 : label is "8";
    attribute PHASEADJ of PLLDInst_0 : label is "0.0";
    attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "25.000000";
    attribute CLKOP_DIV of PLLDInst_0 : label is "8";
    attribute CLKFB_DIV of PLLDInst_0 : label is "4";
    attribute CLKI_DIV of PLLDInst_0 : label is "1";
    attribute FIN of PLLDInst_0 : label is "25.000000";
    attribute syn_keep : boolean;
    attribute syn_noprune : boolean;
    attribute syn_noprune of Structure : architecture is true;

begin
    -- component instantiation statements
    scuba_vlo_inst: VLO
        port map (Z=>scuba_vlo);

    PLLDInst_0: EHXPLLD
        -- synopsys translate_off
        generic map (CLKOK_BYPASS=> "DISABLED", CLKOK_DIV=>  2, 
        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", DELAY_CNTL=> "STATIC", 
        PHASE_CNTL=> "STATIC", FDEL=>  0, DUTY=>  8, PHASEADJ=> "0.0", 
        CLKOP_DIV=>  8, CLKFB_DIV=>  4, CLKI_DIV=>  1)
        -- synopsys translate_on
        port map (CLKI=>CLK_t, CLKFB=>CLKFB_t, RST=>RESET, 
            RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo, 
            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
            DFPAI0=>scuba_vlo, DDAMODE=>scuba_vlo, DDAIZR=>scuba_vlo, 
            DDAILAG=>scuba_vlo, DDAIDEL0=>scuba_vlo, DDAIDEL1=>scuba_vlo, 
            DDAIDEL2=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, 
            CLKOK=>CLKOK, LOCK=>LOCK, CLKINTFB=>CLKFB_t);

    CLKOP <= CLKOP_t;
    CLK_t <= CLK;
end Structure;

-- synopsys translate_off
library ecp2;
configuration Structure_CON of My_pll is
    for Structure
        for all:VLO use entity ecp2.VLO(V); end for;
        for all:EHXPLLD use entity ecp2.EHXPLLD(V); end for;
    end for;
end Structure_CON;

-- synopsys translate_on