mico8.srp

Lattice 超精简8位软核CPU--Mico8

# Info: [44508]: Module work.RC5_RX_M8(behave){generic map (clock => 50000000)}: Compiling...
# Info: [44508]: Module work.LCD_M8(behave): Compiling...
# Info: [44508]: Module work.TX_UART_M8(Behave){generic map (CLKFREQ => 50000000 BAUDRATE => 9600)}: Compiling...
# Info: [44838]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/tx_uart_M8.vhd", line 165: Macro Selcounter "selcounter_13_13_13_0_1_flatten" inferred for node "timecounter".
# Info: [44838]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/tx_uart_M8.vhd", line 211: Macro Modgen_Counter "counter_up_sclear_aclear_clock_clk_en_0_4" inferred for node "bitcounter".
# Info: [44508]: Module work.led_M8(behave): Compiling...
# Info: [44508]: Module work.pwm_M8(behave): Compiling...
# Info: [44838]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/pwm_m8.vhd", line 101: Macro Modgen_Counter "counter_up_sclear_aclear_clock_0_16" inferred for node "counter".
# Info: [44508]: Module work.serout_M8(behave): Compiling...
# Info: [44838]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/SEROUT_M8.vhd", line 96: Macro Modgen_Counter "counter_dn_sload_aclear_clock_clk_en_cnt_en_0_4" inferred for node "shift_cnt".
# Info: [44508]: Module work.ProgPRom(Structure): Compiling...
# Info: [44508]: Module work.My_pll(Structure): Compiling...
# Info: [44508]: Module work.Sys_Cntrl(behaviour): Compiling...
# Info: [44523]: Root Module work.MICO8(SCHEMATIC): Compiling...
# Warning: [45732]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/int_handl_m8.vhd", line 192: Net INT_Set is unused after optimization
# Warning: [45581]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/int_handl_m8.vhd", line 192: No Set/Reset assignment to signal Mico8_INT. Please check if this was not intended.
# Warning: [45581]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/seg7_m8.vhd", line 83: No Set/Reset assignment to signal zWR. Please check if this was not intended.
# Warning: [45581]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/lcd_m8.vhd", line 81: No Set/Reset assignment to signal zWR. Please check if this was not intended.
# Warning: [45581]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/tx_uart_M8.vhd", line 141: No Set/Reset assignment to signal TX_Req. Please check if this was not intended.
# Warning: [45581]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/led_m8.vhd", line 75: No Set/Reset assignment to signal zWR. Please check if this was not intended.
# Warning: [45733]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/pwm_m8.vhd", line 77: Optimizing register bit(s) duty[15:8] to constant 0
# Warning: [45581]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/pwm_m8.vhd", line 77: No Set/Reset assignment to signal zWR. Please check if this was not intended.
# Warning: [45581]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/SEROUT_M8.vhd", line 78: No Set/Reset assignment to signal zWR. Please check if this was not intended.
# Warning: [45581]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/SEROUT_M8.vhd", line 78: No Set/Reset assignment to signal dserdata[7:0]. Please check if this was not intended.
# Info: [44842]: Compilation successfully completed.
# Info: [44841]: Counter Inferencing === Detected : 11, Inferred (Modgen/Selcounter/AddSub) : 8 (6 / 2 / 0), AcrossDH (Merged/Not-Mergred) : (0 / 0), Not-Inferred (Acrossdh/Attempted) : (0 / 1), Local Vars : 2 ===
# Info: [44835]: Total CPU time taken for compilation: 4.2 secs.
# Info: [44856]: Total lines of RTL compiled: 3277.
# Warning: [4554]: Found black-box: work.pmi_distributed_spram_RTLC_LONGENT2; "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/isp8_cfg5.vhd", line 168:.
# Warning: [4554]: Found black-box: work.pmi_distributed_dpram_RTLC_LONGENT1; "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/isp8_core.vhd", line 578:.
# Warning: [4554]: Found black-box: work.pmi_distributed_spram_RTLC_LONGENT0; "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/isp8_flow_cntl.vhd", line 342:.
# Warning: [4554]: Found black-box: work.pmi_addsub_8_8_l1_r3_111_102_102_l1_r2_88_79_l1_r10_112_109_105_95_97_100_100_115_117_98; "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/isp8_alu.vhd", line 108:.
# Info: [634]: Current working directory: c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/mico8_temp_1/.
# Info: [9063]: D-Flipflop instance:I75.reg_PER3_REG(7) with async controls is always disabled
# Info: [9064]: D-Flipflop instance:I75.reg_PER3_REG(7) is converted from DFFE to DFF
# Info: [9063]: D-Flipflop instance:I75.reg_PER3_REG(6) with async controls is always disabled
# Info: [9064]: D-Flipflop instance:I75.reg_PER3_REG(6) is converted from DFFE to DFF
# Info: [9063]: D-Flipflop instance:I75.reg_PER3_REG(5) with async controls is always disabled
# Info: [9064]: D-Flipflop instance:I75.reg_PER3_REG(5) is converted from DFFE to DFF
# Info: [9063]: D-Flipflop instance:I75.reg_PER3_REG(4) with async controls is always disabled
# Info: [9064]: D-Flipflop instance:I75.reg_PER3_REG(4) is converted from DFFE to DFF
# Info: [9063]: D-Flipflop instance:I75.reg_PER3_REG(3) with async controls is always disabled
# Info: [9064]: D-Flipflop instance:I75.reg_PER3_REG(3) is converted from DFFE to DFF
# Info: [9063]: D-Flipflop instance:I75.reg_PER3_REG(2) with async controls is always disabled
# Info: [9064]: D-Flipflop instance:I75.reg_PER3_REG(2) is converted from DFFE to DFF
# Info: [9063]: D-Flipflop instance:I75.reg_PER3_REG(1) with async controls is always disabled
# Info: [9064]: D-Flipflop instance:I75.reg_PER3_REG(1) is converted from DFFE to DFF
# Info: [9063]: D-Flipflop instance:I75.reg_PER3_REG(0) with async controls is always disabled
# Info: [9064]: D-Flipflop instance:I75.reg_PER3_REG(0) is converted from DFFE to DFF
# Info: [9027]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/RX_uart_M8.vhd", line 148: : Inferred selective counter Instance 'instance:I77.ix18' of type 'cell:selcounter_13_13_13_0_1_dn'
# Info: [9027]: "c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/tx_uart_M8.vhd", line 165: : Inferred selective counter Instance 'instance:I72.ix32' of type 'cell:selcounter_13_13_13_0_1_dn'
# Info: [637]: Finished compiling design.
# Info: [634]: Current working directory: c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/mico8_temp_1/.
# Info: [4552]: 1 Instances are flattened in hierarchical block .work.isp8_core_l1_r2_88_79_8_8_9_512_0_4_16.behave_unfold_1530.
# Info: [4552]: 7 Instances are flattened in hierarchical block .work.MICO8.SCHEMATIC.
# Info: [15002]: Optimizing design view:.work.RX_UART_M8_50000000_9600.behave
# Info: [15002]: Optimizing design view:.work.INT_Handl_M8.behave_unfold_830
# Info: [15002]: Optimizing design view:.work.Seg7_M8.behave
# Info: [15002]: Optimizing design view:.work.RC5_RX_M8_50000000.behave_unfold_828
# Info: [15002]: Optimizing design view:.work.TX_UART_M8_50000000_9600.Behave_unfold_795
# Info: [15002]: Optimizing design view:.work.pwm_M8.behave
# Info: [15002]: Optimizing design view:.work.isp8_idec_9.behave_unfold_3124
# Info: [15002]: Optimizing design view:.work.isp8_alu_l1_r2_88_79.behave_unfold_3073
# Info: [15002]: Optimizing design view:.work.isp8_flow_cntl_9_l1_r2_88_79_4_16.behave_unfold_3527
# Info: [15002]: Optimizing design view:.work.isp8_core_l1_r2_88_79_8_8_9_512_0_4_16.behave_unfold_1530
# Info: [15002]: Optimizing design view:.work.MICO8.SCHEMATIC
# Info: [12041]: -- Running timing characterization...
# Warning: [12006]: Timer notification: No timing arcs found for model 'EHXPLLD' in technology 'lattice_ecp2'.
# Warning:     Creating black box model..
# Warning: [1505]: Delay model for work:pmi_addsub_8_8_l1_r3_111_102_102_l1_r2_88_79_l1_r10_112_109_105_95_97_100_100_115_117_98 not specified.
# Warning: [12006]: Timer notification: No timing arcs found for model 'pmi_addsub_8_8_l1_r3_111_102_102_l1_r2_88_79_l1_r10_112_109_105_95_97_100_100_115_117_98' in technology 'work'.
# Warning:     Creating black box model..
# Warning: [1505]: Delay model for work:pmi_distributed_spram_RTLC_LONGENT0 not specified.
# Warning: [12006]: Timer notification: No timing arcs found for model 'pmi_distributed_spram_RTLC_LONGENT0' in technology 'work'.
# Warning:     Creating black box model..
# Warning: [1505]: Delay model for work:pmi_distributed_dpram_RTLC_LONGENT1 not specified.
# Warning: [12006]: Timer notification: No timing arcs found for model 'pmi_distributed_dpram_RTLC_LONGENT1' in technology 'work'.
# Warning:     Creating black box model..
# Warning: [1505]: Delay model for work:pmi_distributed_spram_RTLC_LONGENT2 not specified.
# Warning: [12006]: Timer notification: No timing arcs found for model 'pmi_distributed_spram_RTLC_LONGENT2' in technology 'work'.
# Warning:     Creating black box model..
# Info: [15002]: Optimizing design view:.work.RX_UART_M8_50000000_9600.behave
# Info: [15002]: Optimizing design view:.work.INT_Handl_M8.behave_unfold_830
# Info: [15002]: Optimizing design view:.work.Seg7_M8.behave
# Info: [15002]: Optimizing design view:.work.RC5_RX_M8_50000000.behave_unfold_828
# Info: [15002]: Optimizing design view:.work.TX_UART_M8_50000000_9600.Behave_unfold_795
# Info: [15002]: Optimizing design view:.work.pwm_M8.behave
# Info: [15002]: Optimizing design view:.work.isp8_idec_9.behave_unfold_3124
# Info: [15002]: Optimizing design view:.work.isp8_alu_l1_r2_88_79.behave_unfold_3073
# Info: [15002]: Optimizing design view:.work.isp8_flow_cntl_9_l1_r2_88_79_4_16.behave_unfold_3527
# Info: [15002]: Optimizing design view:.work.isp8_core_l1_r2_88_79_8_8_9_512_0_4_16.behave_unfold_1530
# Info: [15002]: Optimizing design view:.work.MICO8.SCHEMATIC
# Info: [9009]: Inferred Net 'Reset' as GSR Net.
# Info: [15085]: -- Running timing optimization for design .work.RX_UART_M8_50000000_9600.behave.
# Info: [12041]: -- Running timing characterization...
# Info: [15085]: -- Running timing optimization for design .work.INT_Handl_M8.behave_unfold_830.
# Info: [15085]: -- Running timing optimization for design .work.Seg7_M8.behave.
# Info: [15085]: -- Running timing optimization for design .work.RC5_RX_M8_50000000.behave_unfold_828.
# Info: [15085]: -- Running timing optimization for design .work.TX_UART_M8_50000000_9600.Behave_unfold_795.
# Info: [15085]: -- Running timing optimization for design .work.pwm_M8.behave.
# Info: [15085]: -- Running timing optimization for design .work.isp8_idec_9.behave_unfold_3124.
# Info: [15085]: -- Running timing optimization for design .work.isp8_alu_l1_r2_88_79.behave_unfold_3073.
# Info: [15085]: -- Running timing optimization for design .work.isp8_flow_cntl_9_l1_r2_88_79_4_16.behave_unfold_3527.
# Info: [15085]: -- Running timing optimization for design .work.isp8_core_l1_r2_88_79_8_8_9_512_0_4_16.behave_unfold_1530.
# Info: [15085]: -- Running timing optimization for design .work.MICO8.SCHEMATIC.
# Info: [634]: Current working directory: c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/mico8_temp_1/.
# Info: [7004]: Start retiming program ...
# Info: [7012]: Phase 1
# Info: [7010]: ....
# Info: [7012]: Phase 2
# Info: [7010]: ....
# Info: [7012]: Phase 3
# Info: [7010]: ..
# Info: [7012]: Phase 4
# Info: [7010]: ..
# Info: [7012]: Phase 5
# Info: [7010]: ..
# Info: [7012]: Phase 6
# Info: [7012]: Total of registers forward retimed across instances :  13
# Info: [7012]: Total of registers backward retimed across instances :  1
# Info: [7012]: Total of DSPs processed       : 0
# Info: [7012]: Total of registers added      : 30
# Info: [7012]: Total of registers removed    : 8
# Info: [7012]: Total of logic elements added : 0
# Info: [7005]: End retiming program ...
# Info: -- Saving the design database in c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/mico8_temp_1/mico8.xdb
# Info: [3026]: Writing file: c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/mico8_temp_1/mico8.edf.
# Info: [637]: Finished synthesizing design.
# Info: [11019]: Total CPU time taken for synthesis: 12.7 secs.
# Info: [11020]: Overall running time 12.7 secs.
# Info: Setup Slack Path Summary
# Info:                 Data                                                                                                                Data
# Info:        Setup    Path                                                                                                                End
# Info: Index  Slack   Delay       Source Clock          Dest. Clock          Data Start Pin                   Data End Pin                 Edge
# Info: -----  ------  ------  --------------------  --------------------  --------------------  -----------------------------------------  ----
# Info:   1    -5.560  10.673  I47/PLLDInst_0/CLKOK  I47/PLLDInst_0/CLKOK  I47/PLLDInst_0/CLKOK  I78_u1_isp8/u1_isp8_flow_cntl/reg_pc(8)/D  Fall
# Info: -- Device: Lattice - LatticeECP2 : LFE2-6E : 7
# Info: -- CTE report summary..
# Info:                   CTE Report Summary
# Info: Analyzing setup constraint violations
# Info:                         All Clocks Report
# Info: 	Clock                : Frequency
# Info: 	------                ----------
# Info: 	I47/PLLDInst_0/CLKOK : 124.1 MHz
# Info: End CTE Report Summary ..... CPU Time Used: 0 sec.
# Info: [9539]: Saved implementation file: c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/mico8_temp_1/mico8_impl.psi.
# Info: [9531]: Created directory: c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/mico8_impl/.
# Info: [9562]: Saved implementation mico8_impl in project c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/mico8.psp.
# Info: [9540]: Saved project file: c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/mico8.psp.
# Info: [9530]: Closed project: c:/projects/reference/mico8_vhdl/mico8_v3/block_mico8_ecp2_6/mico8.psp.