my_pll_tmpl.vhd

来自「Lattice 超精简8位软核CPU--Mico8」· VHDL 代码 · 共 14 行

-- VHDL module instantiation generated by SCUBA ispLever_v70_SP2_Build (24)
-- Module  Version: 3.7
-- Mon Mar 10 15:41:50 2008

-- parameterized module component declaration
component My_pll
    port (CLK: in std_logic; RESET: in std_logic; CLKOP: out std_logic; 
        CLKOK: out std_logic; LOCK: out std_logic);
end component;

-- parameterized module component instance
__ : My_pll
    port map (CLK=>__, RESET=>__, CLKOP=>__, CLKOK=>__, LOCK=>__);