mico8.drc

Lattice 超精简8位软核CPU--Mico8

INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The
use of the EBR block asynchronous reset requires that certain timing be met
between the clock and the reset within the memory block. See the device
specific datasheet for additional details.
INFO: Design contains pre-loadable EBR during configuration that has a
requirement:Since the GSR is disabled for the EBR, make sure write enable
and chip enable are inactive during wake-up, so that the pre-loaded
initialization values will not be corrupted during wake-up state.
DRC detected 0 errors and 0 warnings.