mico8.vm

Lattice 超精简8位软核CPU--Mico8

  FD1S3AX \ext_addr_Z[2]  (
	.D(ext_addr_4[2]),
	.CK(MicoCLK),
	.Q(MicoAddr[2])
);
// @4:86
  FD1S3AX \ext_addr_Z[3]  (
	.D(ext_addr_4[3]),
	.CK(MicoCLK),
	.Q(MicoAddr[3])
);
// @4:86
  FD1S3AX \ext_addr_Z[4]  (
	.D(ext_addr_4[4]),
	.CK(MicoCLK),
	.Q(MicoAddr[4])
);
// @4:86
  FD1S3AX \ext_addr_Z[5]  (
	.D(ext_addr_4[5]),
	.CK(MicoCLK),
	.Q(MicoAddr[5])
);
// @4:86
  FD1S3AX \ext_addr_Z[6]  (
	.D(ext_addr_4[6]),
	.CK(MicoCLK),
	.Q(MicoAddr[6])
);
// @4:86
  FD1S3AX \ext_addr_Z[7]  (
	.D(ext_addr_4[7]),
	.CK(MicoCLK),
	.Q(MicoAddr[7])
);
assign addr_cyc_int_1_1 = (~addr_cyc & ~ext_addr_cyc_int_Q);
assign ext_addr_4[0] = (dout_rb[0] & un6_export_i) | (dout_rb[0] & un6_export_i & 
   ~Mico8_Instr_3) | (dout_rb[0] & Mico8_Instr_3) | (~un6_export_i & Mico8_Instr_3) | 
   (dout_rb[0] & un6_export_i & Mico8_Instr_3);
assign ext_addr_4[1] = (dout_rb[1] & un6_export_i) | (dout_rb[1] & un6_export_i & 
   ~Mico8_Instr_4) | (dout_rb[1] & Mico8_Instr_4) | (~un6_export_i & Mico8_Instr_4) | 
   (dout_rb[1] & un6_export_i & Mico8_Instr_4);
assign ext_addr_4[2] = (dout_rb[2] & un6_export_i) | (dout_rb[2] & un6_export_i & 
   ~Mico8_Instr_5) | (dout_rb[2] & Mico8_Instr_5) | (~un6_export_i & Mico8_Instr_5) | 
   (dout_rb[2] & un6_export_i & Mico8_Instr_5);
assign ext_addr_4[3] = (dout_rb[3] & un6_export_i) | (dout_rb[3] & un6_export_i & 
   ~Mico8_Instr_6) | (dout_rb[3] & Mico8_Instr_6) | (~un6_export_i & Mico8_Instr_6) | 
   (dout_rb[3] & un6_export_i & Mico8_Instr_6);
assign ext_addr_4[4] = (dout_rb[4] & un6_export_i) | (dout_rb[4] & un6_export_i & 
   ~Mico8_Instr_7) | (dout_rb[4] & Mico8_Instr_7) | (~un6_export_i & Mico8_Instr_7) | 
   (dout_rb[4] & un6_export_i & Mico8_Instr_7);
assign un6_export_i = (~iels_ie & ~iels_ls) | (~iels_ie & ~iels_ls & ~Mico8_Instr_1) | 
   (Mico8_Instr_1);
  assign NN_1 = 1'b0;
  assign VCC = 1'b1;
endmodule /* isp8_io_cntl */

module isp8_core (
  MicoDOut,
  MicoAddr,
  Mico8_Data_i_2_3,
  Mico8_Data_i_2_2,
  Mico8_Data_i_2_0,
  Mico8_Data_i_1,
  Mico8_Instr,
  ext_mem_din,
  ext_mem_wr,
  Mico_WR_c,
  Mico_RD_c,
  zero_flag,
  intr_reg0,
  g0_7,
  INTAck_c,
  sp_we_1_i_o2_N_14_i,
  N_302_i,
  N_304_i,
  N_305_i,
  N_306_i,
  N_307_i,
  N_51_i,
  N_53_i,
  br_enb_0_a2_0_0,
  prom_addr_1_16_i_i_a2_s_0_N_5,
  N_303_i,
  Mico_Int_c,
  N_301_i,
  carry_flag,
  instr_l2_1,
  VCC,
  N_290,
  N_298,
  N_303,
  data_cyc_int,
  nReset_c,
  MicoCLK,
  GND
)
;
output [7:0] MicoDOut ;
output [7:0] MicoAddr ;
input Mico8_Data_i_2_3 ;
input Mico8_Data_i_2_2 ;
input Mico8_Data_i_2_0 ;
input [7:4] Mico8_Data_i_1 ;
input [17:0] Mico8_Instr ;
input [7:0] ext_mem_din ;
output ext_mem_wr ;
output Mico_WR_c ;
output Mico_RD_c ;
output zero_flag ;
output intr_reg0 ;
input g0_7 ;
output INTAck_c ;
output sp_we_1_i_o2_N_14_i ;
output N_302_i ;
output N_304_i ;
output N_305_i ;
output N_306_i ;
output N_307_i ;
output N_51_i ;
output N_53_i ;
input br_enb_0_a2_0_0 ;
input prom_addr_1_16_i_i_a2_s_0_N_5 ;
output N_303_i ;
input Mico_Int_c ;
output N_301_i ;
output carry_flag ;
input instr_l2_1 ;
input VCC ;
input N_290 ;
input N_298 ;
input N_303 ;
output data_cyc_int ;
input nReset_c ;
input MicoCLK ;
input GND ;
wire Mico8_Data_i_2_3 ;
wire Mico8_Data_i_2_2 ;
wire Mico8_Data_i_2_0 ;
wire ext_mem_wr ;
wire Mico_WR_c ;
wire Mico_RD_c ;
wire zero_flag ;
wire intr_reg0 ;
wire g0_7 ;
wire INTAck_c ;
wire sp_we_1_i_o2_N_14_i ;
wire N_302_i ;
wire N_304_i ;
wire N_305_i ;
wire N_306_i ;
wire N_307_i ;
wire N_51_i ;
wire N_53_i ;
wire br_enb_0_a2_0_0 ;
wire prom_addr_1_16_i_i_a2_s_0_N_5 ;
wire N_303_i ;
wire Mico_Int_c ;
wire N_301_i ;
wire carry_flag ;
wire instr_l2_1 ;
wire VCC ;
wire N_290 ;
wire N_298 ;
wire N_303 ;
wire data_cyc_int ;
wire nReset_c ;
wire MicoCLK ;
wire GND ;
wire [7:0] din_rd;
wire [7:0] din_rd1;
wire [1:1] din_rd_0_d;
wire [7:0] dout_alu;
wire [7:0] din_rd1_QN;
wire [7:0] dout_rd;
wire [7:0] dout_rb;
wire N_6 ;
wire iels_ls ;
wire N_5 ;
wire N_3 ;
wire N_10 ;
wire N_9 ;
wire N_8 ;
wire N_7 ;
wire N_284_2 ;
wire N_27_i ;
wire wren_il_rd ;
wire wren_il_rd_QN ;
wire N_26_i ;
wire wren_alu_rd ;
wire wren_alu_rd_QN ;
wire wren_rd ;
wire re_1 ;
wire N_284_3 ;
wire iels_ie ;
wire clri_i ;
wire clrc ;
wire setc ;
wire setz ;
wire update_c_i ;
wire update_z_0 ;
wire ca0 ;
wire call ;
wire iels ;
wire iret ;
wire update_z_1 ;
wire N_36_1 ;
wire un1_br0 ;
wire re ;
wire sub ;
wire sc ;
wire instr_l1_3 ;
wire N_221 ;
wire instr_l2_3 ;
wire cout_alu_u_0_1 ;
wire N_140 ;
wire addr_cyc_int_1_1 ;
wire ext_addr_cyc_int_Q ;
wire addr_cyc ;
wire NN_1 ;
wire NN_2 ;
assign din_rd[3] = (N_6 & ext_mem_din[3]) | (N_6 & ~Mico8_Instr[0]) | (N_6 & 
   ext_mem_din[3] & Mico8_Instr[0]) | (N_6 & ~iels_ls) | (N_6 & ext_mem_din[3] & 
   iels_ls) | (N_6 & ~Mico8_Instr[0] & iels_ls) | (ext_mem_din[3] & Mico8_Instr[0] & 
   iels_ls);
assign din_rd[2] = (N_5 & ext_mem_din[2]) | (N_5 & ~Mico8_Instr[0]) | (N_5 & 
   ext_mem_din[2] & Mico8_Instr[0]) | (N_5 & ~iels_ls) | (N_5 & ext_mem_din[2] & 
   iels_ls) | (N_5 & ~Mico8_Instr[0] & iels_ls) | (ext_mem_din[2] & Mico8_Instr[0] & 
   iels_ls);
assign din_rd[0] = (N_3 & ext_mem_din[0]) | (N_3 & ~Mico8_Instr[0]) | (N_3 & 
   ext_mem_din[0] & Mico8_Instr[0]) | (N_3 & ~iels_ls) | (N_3 & ext_mem_din[0] & 
   iels_ls) | (N_3 & ~Mico8_Instr[0] & iels_ls) | (ext_mem_din[0] & Mico8_Instr[0] & 
   iels_ls);
assign din_rd[7] = (N_10 & ext_mem_din[7]) | (N_10 & ~Mico8_Instr[0]) | 
   (N_10 & ext_mem_din[7] & Mico8_Instr[0]) | (N_10 & ~iels_ls) | (N_10 & 
   ext_mem_din[7] & iels_ls) | (N_10 & ~Mico8_Instr[0] & iels_ls) | (ext_mem_din[7] & 
   Mico8_Instr[0] & iels_ls);
assign din_rd[6] = (N_9 & ext_mem_din[6]) | (N_9 & ~Mico8_Instr[0]) | (N_9 & 
   ext_mem_din[6] & Mico8_Instr[0]) | (N_9 & ~iels_ls) | (N_9 & ext_mem_din[6] & 
   iels_ls) | (N_9 & ~Mico8_Instr[0] & iels_ls) | (ext_mem_din[6] & Mico8_Instr[0] & 
   iels_ls);
assign din_rd[5] = (N_8 & ext_mem_din[5]) | (N_8 & ~Mico8_Instr[0]) | (N_8 & 
   ext_mem_din[5] & Mico8_Instr[0]) | (N_8 & ~iels_ls) | (N_8 & ext_mem_din[5] & 
   iels_ls) | (N_8 & ~Mico8_Instr[0] & iels_ls) | (ext_mem_din[5] & Mico8_Instr[0] & 
   iels_ls);
assign din_rd[4] = (N_7 & ext_mem_din[4]) | (N_7 & ~Mico8_Instr[0]) | (N_7 & 
   ext_mem_din[4] & Mico8_Instr[0]) | (N_7 & ~iels_ls) | (N_7 & ext_mem_din[4] & 
   iels_ls) | (N_7 & ~Mico8_Instr[0] & iels_ls) | (ext_mem_din[4] & Mico8_Instr[0] & 
   iels_ls);
assign N_27_i = (~N_284_2) | (~N_284_2 & ~iels_ls) | (~N_284_2 & iels_ls) | 
   (~N_284_2 & ~Mico8_Instr[0] & iels_ls) | (Mico8_Instr[0] & iels_ls);
assign din_rd_0_d[1] = (din_rd1[1] & ext_mem_din[1]) | (din_rd1[1] & ~Mico8_Instr[0]) | 
   (din_rd1[1] & ext_mem_din[1] & Mico8_Instr[0]) | (din_rd1[1] & ~iels_ls) | 
   (din_rd1[1] & ext_mem_din[1] & iels_ls) | (din_rd1[1] & ~Mico8_Instr[0] & 
   iels_ls) | (ext_mem_din[1] & Mico8_Instr[0] & iels_ls);
// @20:629
  FD1S3AX wren_il_rd_Z (
	.D(N_27_i),
	.CK(MicoCLK),
	.Q(wren_il_rd)
);
// @20:629
  FD1S3AX wren_alu_rd_Z (
	.D(N_26_i),
	.CK(MicoCLK),
	.Q(wren_alu_rd)
);
// @20:641
  FD1S3AX \din_rd1_Z[0]  (
	.D(dout_alu[0]),
	.CK(MicoCLK),
	.Q(din_rd1[0])
);
// @20:641
  FD1S3AX \din_rd1_Z[1]  (
	.D(dout_alu[1]),
	.CK(MicoCLK),
	.Q(din_rd1[1])
);
// @20:641
  FD1S3AX \din_rd1_Z[2]  (
	.D(dout_alu[2]),
	.CK(MicoCLK),
	.Q(din_rd1[2])
);
// @20:641
  FD1S3AX \din_rd1_Z[3]  (
	.D(dout_alu[3]),
	.CK(MicoCLK),
	.Q(din_rd1[3])
);
// @20:641
  FD1S3AX \din_rd1_Z[4]  (
	.D(dout_alu[4]),
	.CK(MicoCLK),
	.Q(din_rd1[4])
);
// @20:641
  FD1S3AX \din_rd1_Z[5]  (
	.D(dout_alu[5]),
	.CK(MicoCLK),
	.Q(din_rd1[5])
);
// @20:641
  FD1S3AX \din_rd1_Z[6]  (
	.D(dout_alu[6]),
	.CK(MicoCLK),
	.Q(din_rd1[6])
);
// @20:641
  FD1S3AX \din_rd1_Z[7]  (
	.D(dout_alu[7]),
	.CK(MicoCLK),
	.Q(din_rd1[7])
);
assign wren_rd = (wren_alu_rd & data_cyc_int) | (wren_alu_rd & ~wren_il_rd & 
   data_cyc_int) | (wren_il_rd & data_cyc_int);
assign N_26_i = (re_1 & ~Mico8_Instr[13] & ~Mico8_Instr[16]) | (~Mico8_Instr[17]) | 
   (re_1 & ~Mico8_Instr[13] & ~Mico8_Instr[16] & Mico8_Instr[17]);
assign N_284_3 = (~iels_ls) | (~Mico8_Instr[0]) | (~iels_ls & Mico8_Instr[0]);
assign N_284_2 = (~iels_ie) | (~Mico8_Instr[0]) | (~iels_ie & Mico8_Instr[0]);
assign N_7 = (~Mico8_Data_i_1[4] & ~N_303 & din_rd1[4]) | (~Mico8_Data_i_1[4] & 
   ~N_303 & ~N_284_2) | (din_rd1[4] & N_284_2);
assign N_8 = (~Mico8_Data_i_1[5] & ~N_303 & din_rd1[5]) | (~Mico8_Data_i_1[5] & 
   ~N_303 & ~N_284_2) | (din_rd1[5] & N_284_2);
assign N_10 = (~Mico8_Data_i_1[7] & ~N_303 & din_rd1[7]) | (~Mico8_Data_i_1[7] & 
   ~N_303 & ~N_284_2) | (din_rd1[7] & N_284_2);
assign N_9 = (~Mico8_Data_i_1[6] & ~N_303 & din_rd1[6]) | (~Mico8_Data_i_1[6] & 
   ~N_303 & ~N_284_2) | (din_rd1[6] & N_284_2);
assign N_3 = (~Mico8_Data_i_2_0 & ~N_298 & din_rd1[0]) | (~Mico8_Data_i_2_0 & 
   ~N_298 & ~N_284_2) | (din_rd1[0] & N_284_2);
assign N_5 = (~Mico8_Data_i_2_2 & ~N_298 & din_rd1[2]) | (~Mico8_Data_i_2_2 & 
   ~N_298 & ~N_284_2) | (din_rd1[2] & N_284_2);
assign N_6 = (~Mico8_Data_i_2_3 & ~N_298 & din_rd1[3]) | (~Mico8_Data_i_2_3 & 
   ~N_298 & ~N_284_2) | (din_rd1[3] & N_284_2);
assign din_rd[1] = (~N_290 & ~N_284_2 & N_284_3) | (~N_290 & ~N_284_2 & 
   N_284_3 & ~din_rd_0_d[1]) | (~N_290 & din_rd_0_d[1]) | (~N_290 & ~N_284_2 & 
   din_rd_0_d[1]) | (N_284_2 & din_rd_0_d[1]) | (~N_284_3 & din_rd_0_d[1]) | 
   (~N_290 & N_284_3 & din_rd_0_d[1]) | (~N_290 & ~N_284_2 & N_284_3 & 
   din_rd_0_d[1]) | (N_284_2 & N_284_3 & din_rd_0_d[1]);
// @20:600
  pmi_distributed_dpram_work_mico8_schematic_1 \GEN_REG_32.u2_isp8_rfmem  (
	.WrAddress({Mico8_Instr[12], Mico8_Instr[11], Mico8_Instr[10], Mico8_Instr[9], 
   Mico8_Instr[8]}),
	.Data({din_rd[7], din_rd[6], din_rd[5], din_rd[4], din_rd[3], din_rd[2], 
   din_rd[1], din_rd[0]}),
	.WrClock(MicoCLK),
	.WE(wren_rd),
	.WrClockEn(VCC),
	.RdAddress({Mico8_Instr[12], Mico8_Instr[11], Mico8_Instr[10], Mico8_Instr[9], 
   Mico8_Instr[8]}),
	.RdClock(MicoCLK),
	.RdClockEn(VCC),
	.Reset(GND),
	.Q({dout_rd[7], dout_rd[6], dout_rd[5], dout_rd[4], dout_rd[3], dout_rd[2], 
   dout_rd[1], dout_rd[0]})
);
defparam \GEN_REG_32.u2_isp8_rfmem .pmi_addr_depth = 32;
defparam \GEN_REG_32.u2_isp8_rfmem .pmi_addr_width = 5;
defparam \GEN_REG_32.u2_isp8_rfmem .pmi_data_width = 8;
defparam \GEN_REG_32.u2_isp8_rfmem .pmi_regmode = "noreg";
defparam \GEN_REG_32.u2_isp8_rfmem .pmi_init_file = "none";
defparam \GEN_REG_32.u2_isp8_rfmem .pmi_init_file_format = "binary";
defparam \GEN_REG_32.u2_isp8_rfmem .pmi_family = "ECP2";
defparam \GEN_REG_32.u2_isp8_rfmem .module_type = "pmi_distributed_dpram";
// @20:578
  pmi_distributed_dpram_work_mico8_schematic_0 \GEN_REG_32.u1_isp8_rfmem  (
	.WrAddress({Mico8_Instr[12], Mico8_Instr[11], Mico8_Instr[10], Mico8_Instr[9], 
   Mico8_Instr[8]}),
	.Data({din_rd[7], din_rd[6], din_rd[5], din_rd[4], din_rd[3], din_rd[2], 
   din_rd[1], din_rd[0]}),
	.WrClock(MicoCLK),
	.WE(wren_rd),
	.WrClockEn(VCC),
	.RdAddr