mico8.vm

Lattice 超精简8位软核CPU--Mico8

   pushed_zero) | (iret & ~setz & ~N_145 & pushed_zero) | (setz & ~N_145 & 
   pushed_zero) | (N_145 & pushed_zero);
assign N_55_i = (~g0_7 & dout_stack[0] & pc_int[0]) | (~g0_7 & pc_int[0] & 
   ~ret_reg) | (~g0_7 & dout_stack[0] & ret_reg);
assign N_303_i = (N_111 & ~br_enb_0_a2_0_0) | (N_111 & ~br_enb_0_a2_0_0 & 
   ~prom_addr_1_16_i_i_a2_s_0_N_5) | (N_111 & prom_addr_1_16_i_i_a2_s_0_N_5) | 
   (N_111 & ~prom_addr_i_0_m5_0_a2_0) | (N_111 & ~br_enb_0_a2_0_0 & prom_addr_i_0_m5_0_a2_0) | 
   (N_111 & ~br_enb_0_a2_0_0 & ~prom_addr_1_16_i_i_a2_s_0_N_5 & prom_addr_i_0_m5_0_a2_0) | 
   (N_111 & prom_addr_1_16_i_i_a2_s_0_N_5 & prom_addr_i_0_m5_0_a2_0);
assign N_22 = (N_129) | (N_129 & ~data_cyc_int) | (N_129 & data_cyc_int) | 
   (N_129 & ~g0_7 & data_cyc_int) | (g0_7 & data_cyc_int);
assign N_24 = (~addr_cyc) | (~addr_cyc & ~prom_addr_i_0_m5_0_a2_0) | (prom_addr_i_0_m5_0_a2_0) | 
   (~addr_cyc & ~un1_addr_cyc_int_i_a2_d[2]) | (~addr_cyc & ~prom_addr_i_0_m5_0_a2_0 & 
   ~un1_addr_cyc_int_i_a2_d[2]) | (prom_addr_i_0_m5_0_a2_0 & ~un1_addr_cyc_int_i_a2_d[2]) | 
   (un1_addr_cyc_int_i_a2_d[2]) | (~re) | (~addr_cyc & re) | (~addr_cyc & 
   ~prom_addr_i_0_m5_0_a2_0 & re) | (prom_addr_i_0_m5_0_a2_0 & re) | (~addr_cyc & 
   ~un1_addr_cyc_int_i_a2_d[2] & re) | (~addr_cyc & ~prom_addr_i_0_m5_0_a2_0 & 
   ~un1_addr_cyc_int_i_a2_d[2] & re) | (prom_addr_i_0_m5_0_a2_0 & ~un1_addr_cyc_int_i_a2_d[2] & 
   re) | (un1_addr_cyc_int_i_a2_d[2] & re);
assign un1_addr_cyc_int_i_a2_1[2] = (prom_addr_i_0_m5_0_a2_0) | (prom_addr_i_0_m5_0_a2_0 & 
   ~un1_addr_cyc_int_i_a2_d[2]) | (un1_addr_cyc_int_i_a2_d[2]) | (prom_addr_i_0_m5_0_a2_0 & 
   ~re) | (prom_addr_i_0_m5_0_a2_0 & ~un1_addr_cyc_int_i_a2_d[2] & ~re) | 
   (un1_addr_cyc_int_i_a2_d[2] & ~re) | (addr_cyc & re) | (addr_cyc & 
   ~prom_addr_i_0_m5_0_a2_0 & re) | (prom_addr_i_0_m5_0_a2_0 & re) | (addr_cyc & 
   ~un1_addr_cyc_int_i_a2_d[2] & re) | (addr_cyc & ~prom_addr_i_0_m5_0_a2_0 & 
   ~un1_addr_cyc_int_i_a2_d[2] & re) | (prom_addr_i_0_m5_0_a2_0 & ~un1_addr_cyc_int_i_a2_d[2] & 
   re) | (un1_addr_cyc_int_i_a2_d[2] & re);
assign N_280_i = (call) | (~br_enb_0_a2_0_0) | (call & br_enb_0_a2_0_0) | 
   (call & ~Mico8_Instr_12) | (~br_enb_0_a2_0_0 & ~Mico8_Instr_12) | (call & 
   br_enb_0_a2_0_0 & ~Mico8_Instr_12) | (call & Mico8_Instr_12) | (~br_enb_0_a2_0_0 & 
   Mico8_Instr_12) | (call & br_enb_0_a2_0_0 & Mico8_Instr_12) | (call & 
   ~un1_br0 & Mico8_Instr_12) | (~br_enb_0_a2_0_0 & ~un1_br0 & Mico8_Instr_12) | 
   (call & br_enb_0_a2_0_0 & ~un1_br0 & Mico8_Instr_12) | (un1_br0 & Mico8_Instr_12);
assign N_286_i = (clrc) | (clrc & ~iret) | (iret) | (clrc & ~setc) | (clrc & 
   ~iret & ~setc) | (iret & ~setc) | (setc) | (~update_c_i) | (clrc & 
   update_c_i) | (clrc & ~iret & update_c_i) | (iret & update_c_i) | (clrc & 
   ~setc & update_c_i) | (clrc & ~iret & ~setc & update_c_i) | (iret & 
   ~setc & update_c_i) | (setc & update_c_i);
assign intr_reg0_1_0_a2_2 = (~call & ie_flag & intr_reg0_1_4 & Mico_Int_c);
assign un1_stack_ptr_axb0 = (un1_addr_cyc_int_i_a2_1[2] & ~stack_ptr[0]) | 
   (~un1_addr_cyc_int_i_a2_1[2] & stack_ptr[0]);
assign N_24_i = (addr_cyc & ~prom_addr_i_0_m5_0_a2_0 & ~un1_addr_cyc_int_i_a2_d[2] & 
   re);
assign N_125 = (~clrc & N_140 & ~update_c_i) | (~clrc & N_140 & ~cout_alu_u_0_1 & 
   ~update_c_i) | (~clrc & cout_alu_u_0_1 & ~update_c_i);
assign un1_stack_ptr_axbxc2 = (~N_24 & ~stack_ptr[2] & ~un1_stack_ptr_p4) | 
   (N_24 & stack_ptr[2] & ~un1_stack_ptr_p4) | (N_24 & ~stack_ptr[2] & 
   un1_stack_ptr_p4) | (~N_24 & stack_ptr[2] & un1_stack_ptr_p4);
assign un1_stack_ptr_axbxc1 = (~N_24 & ~un1_addr_cyc_int_i_a2_1[2] & ~stack_ptr[1]) | 
   (~N_24 & ~stack_ptr[0] & ~stack_ptr[1]) | (~N_24 & ~un1_addr_cyc_int_i_a2_1[2] & 
   stack_ptr[0] & ~stack_ptr[1]) | (N_24 & un1_addr_cyc_int_i_a2_1[2] & 
   stack_ptr[0] & ~stack_ptr[1]) | (N_24 & ~un1_addr_cyc_int_i_a2_1[2] & 
   stack_ptr[1]) | (N_24 & ~stack_ptr[0] & stack_ptr[1]) | (N_24 & ~un1_addr_cyc_int_i_a2_1[2] & 
   stack_ptr[0] & stack_ptr[1]) | (~N_24 & un1_addr_cyc_int_i_a2_1[2] & 
   stack_ptr[0] & stack_ptr[1]);
assign carry_flag_int_1_1 = (setc) | (setc & ~N_125) | (N_125) | (setc & 
   ~pushed_carry) | (setc & ~N_125 & ~pushed_carry) | (N_125 & ~pushed_carry) | 
   (iret & pushed_carry) | (iret & ~setc & pushed_carry) | (setc & pushed_carry) | 
   (iret & ~N_125 & pushed_carry) | (iret & ~setc & ~N_125 & pushed_carry) | 
   (setc & ~N_125 & pushed_carry) | (N_125 & pushed_carry);
assign N_301_i = (N_108 & ~br_enb_0_a2_0_0) | (N_108 & ~br_enb_0_a2_0_0 & 
   ~prom_addr_1_16_i_i_a2_s_0_N_5) | (N_108 & prom_addr_1_16_i_i_a2_s_0_N_5) | 
   (N_108 & ~prom_addr_i_0_m5_0_a2_0) | (N_108 & ~br_enb_0_a2_0_0 & prom_addr_i_0_m5_0_a2_0) | 
   (N_108 & ~br_enb_0_a2_0_0 & ~prom_addr_1_16_i_i_a2_s_0_N_5 & prom_addr_i_0_m5_0_a2_0) | 
   (N_108 & prom_addr_1_16_i_i_a2_s_0_N_5 & prom_addr_i_0_m5_0_a2_0);
assign intr_reg0_1 = (intr_reg0_1_0_a2_2 & intr_reg0_1_1_tz) | (intr_reg0_1_0_a2_2 & 
   intr_reg0_1_1_tz & ~Mico8_Instr_11) | (intr_reg0_1_0_a2_2 & intr_reg0_1_1_tz & 
   Mico8_Instr_11) | (intr_reg0_1_0_a2_2 & intr_reg0_1_1_tz & ~Mico8_Instr_10 & 
   Mico8_Instr_11) | (intr_reg0_1_0_a2_2 & Mico8_Instr_10 & Mico8_Instr_11);
assign un1_stack_ptr_axbxc3_1 = (N_24 & ~stack_ptr[3]) | (~N_24 & stack_ptr[3]);
assign un1_stack_ptr_axbxc3 = (~N_24_i & ~stack_ptr[2] & ~un1_stack_ptr_axbxc3_1) | 
   (N_24_i & stack_ptr[2] & un1_stack_ptr_axbxc3_1) | (~N_24_i & ~un1_stack_ptr_axbxc3_1 & 
   ~un1_stack_ptr_p4) | (~stack_ptr[2] & ~un1_stack_ptr_axbxc3_1 & ~un1_stack_ptr_p4) | 
   (~N_24_i & stack_ptr[2] & ~un1_stack_ptr_axbxc3_1 & ~un1_stack_ptr_p4) | 
   (N_24_i & stack_ptr[2] & un1_stack_ptr_axbxc3_1 & ~un1_stack_ptr_p4) | 
   (~N_24_i & ~stack_ptr[2] & ~un1_stack_ptr_axbxc3_1 & un1_stack_ptr_p4) | 
   (N_24_i & un1_stack_ptr_axbxc3_1 & un1_stack_ptr_p4) | (N_24_i & ~stack_ptr[2] & 
   un1_stack_ptr_axbxc3_1 & un1_stack_ptr_p4) | (stack_ptr[2] & un1_stack_ptr_axbxc3_1 & 
   un1_stack_ptr_p4);
assign un1_addr_cyc_int_i_a2_d_0_1[2] = (Mico8_Instr_13 & Mico8_Instr_14 & 
   ~Mico8_Instr_15 & data_cyc_int);
assign un1_addr_cyc_int_i_a2_d[2] = (sp_we_1_i_o2_N_14_i & un1_addr_cyc_int_i_a2_d_0_1[2] & 
   instr_l1_3) | (sp_we_1_i_o2_N_14_i & un1_addr_cyc_int_i_a2_d_0_1[2] & 
   instr_l1_3 & ~Mico8_Instr_12) | (un1_addr_cyc_int_i_a2_d_0_1[2] & instr_l1_3 & 
   Mico8_Instr_12);
// @5:234
  CCU2B pc_int_cry_7_0 (
	.A0(N_157),
	.B0(addr_jmp_reg[7]),
	.C0(pc[7]),
	.D0(VCC),
	.A1(pc[8]),
	.B1(addr_jmp_reg[8]),
	.C1(N_157),
	.D1(VCC),
	.CIN(pc_int_cry_6),
	.COUT(pc_int_cry_7_0_COUT),
	.S0(pc_int[7]),
	.S1(pc_int[8])
);
defparam pc_int_cry_7_0.INIT0=16'h7808;
defparam pc_int_cry_7_0.INIT1=16'h6a0a;
defparam pc_int_cry_7_0.INJECT1_0="NO";
defparam pc_int_cry_7_0.INJECT1_1="NO";
// @5:234
  CCU2B pc_int_cry_5_0 (
	.A0(N_157),
	.B0(addr_jmp_reg[5]),
	.C0(pc[5]),
	.D0(VCC),
	.A1(N_157),
	.B1(addr_jmp_reg[6]),
	.C1(pc[6]),
	.D1(VCC),
	.CIN(pc_int_cry_4),
	.COUT(pc_int_cry_6),
	.S0(pc_int[5]),
	.S1(pc_int[6])
);
defparam pc_int_cry_5_0.INIT0=16'h7808;
defparam pc_int_cry_5_0.INIT1=16'h7808;
defparam pc_int_cry_5_0.INJECT1_0="NO";
defparam pc_int_cry_5_0.INJECT1_1="NO";
// @5:234
  CCU2B pc_int_cry_3_0 (
	.A0(N_157),
	.B0(addr_jmp_reg[3]),
	.C0(pc[3]),
	.D0(VCC),
	.A1(N_157),
	.B1(addr_jmp_reg[4]),
	.C1(pc[4]),
	.D1(VCC),
	.CIN(pc_int_cry_2),
	.COUT(pc_int_cry_4),
	.S0(pc_int[3]),
	.S1(pc_int[4])
);
defparam pc_int_cry_3_0.INIT0=16'h7808;
defparam pc_int_cry_3_0.INIT1=16'h7808;
defparam pc_int_cry_3_0.INJECT1_0="NO";
defparam pc_int_cry_3_0.INJECT1_1="NO";
// @5:234
  CCU2B pc_int_cry_1_0 (
	.A0(N_157),
	.B0(addr_jmp_reg[1]),
	.C0(pc[1]),
	.D0(VCC),
	.A1(N_157),
	.B1(addr_jmp_reg[2]),
	.C1(pc[2]),
	.D1(VCC),
	.CIN(pc_int_cry_0),
	.COUT(pc_int_cry_2),
	.S0(pc_int[1]),
	.S1(pc_int[2])
);
defparam pc_int_cry_1_0.INIT0=16'h7808;
defparam pc_int_cry_1_0.INIT1=16'h7808;
defparam pc_int_cry_1_0.INJECT1_0="NO";
defparam pc_int_cry_1_0.INJECT1_1="NO";
  CCU2B pc_int_cry_0_0 (
	.A0(GND),
	.B0(GND),
	.C0(GND),
	.D0(VCC),
	.A1(pc[0]),
	.B1(addr_jmp_reg[0]),
	.C1(N_157),
	.D1(VCC),
	.CIN(GND),
	.COUT(pc_int_cry_0),
	.S0(pc_int_cry_0_0_S0),
	.S1(pc_int_cry_0_0_S1)
);
defparam pc_int_cry_0_0.INIT0=16'h0a0c;
defparam pc_int_cry_0_0.INIT1=16'h650a;
defparam pc_int_cry_0_0.INJECT1_0="NO";
defparam pc_int_cry_0_0.INJECT1_1="NO";
// @5:342
  pmi_distributed_spram_work_mico8_schematic_1 u1_isp8_stkmem (
	.Address({stack_ptr[3], stack_ptr[2], stack_ptr[1], stack_ptr[0]}),
	.Data({carry_flag, zero_flag, pc_int[8], pc_int[7], pc_int[6], pc_int[5], 
   pc_int[4], pc_int[3], pc_int[2], pc_int[1], pc_int[0]}),
	.Clock(MicoCLK),
	.ClockEn(VCC),
	.WE(N_22),
	.Reset(GND),
	.Q({pushed_carry, pushed_zero, dout_stack[8], dout_stack[7], dout_stack[6], 
   dout_stack[5], dout_stack[4], dout_stack[3], dout_stack[2], dout_stack[1], 
   dout_stack[0]})
);
defparam u1_isp8_stkmem.pmi_addr_depth = 16;
defparam u1_isp8_stkmem.pmi_addr_width = 4;
defparam u1_isp8_stkmem.pmi_data_width = 11;
defparam u1_isp8_stkmem.pmi_regmode = "noreg";
defparam u1_isp8_stkmem.pmi_init_file = "none";
defparam u1_isp8_stkmem.pmi_init_file_format = "binary";
defparam u1_isp8_stkmem.pmi_family = "ECP2";
  assign NN_1 = 1'b0;
  assign NN_2 = 1'b1;
endmodule /* isp8_flow_cntl */

module isp8_io_cntl (
  MicoAddr,
  MicoDOut,
  dout_rd,
  dout_rb,
  Mico8_Instr_7,
  Mico8_Instr_6,
  Mico8_Instr_5,
  Mico8_Instr_4,
  Mico8_Instr_3,
  Mico8_Instr_1,
  Mico8_Instr_0,
  addr_cyc_int_1_1,
  GND,
  Mico_RD_c,
  Mico_WR_c,
  nReset_c,
  ext_mem_wr,
  MicoCLK,
  iels_ls,
  addr_cyc,
  ext_addr_cyc_int_Q,
  iels_ie
)
;
output [7:0] MicoAddr ;
output [7:0] MicoDOut ;
input [7:0] dout_rd ;
input [7:0] dout_rb ;
input Mico8_Instr_7 ;
input Mico8_Instr_6 ;
input Mico8_Instr_5 ;
input Mico8_Instr_4 ;
input Mico8_Instr_3 ;
input Mico8_Instr_1 ;
input Mico8_Instr_0 ;
output addr_cyc_int_1_1 ;
input GND ;
output Mico_RD_c ;
output Mico_WR_c ;
input nReset_c ;
output ext_mem_wr ;
input MicoCLK ;
input iels_ls ;
input addr_cyc ;
input ext_addr_cyc_int_Q ;
input iels_ie ;
wire Mico8_Instr_7 ;
wire Mico8_Instr_6 ;
wire Mico8_Instr_5 ;
wire Mico8_Instr_4 ;
wire Mico8_Instr_3 ;
wire Mico8_Instr_1 ;
wire Mico8_Instr_0 ;
wire addr_cyc_int_1_1 ;
wire GND ;
wire Mico_RD_c ;
wire Mico_WR_c ;
wire nReset_c ;
wire ext_mem_wr ;
wire MicoCLK ;
wire iels_ls ;
wire addr_cyc ;
wire ext_addr_cyc_int_Q ;
wire iels_ie ;
wire [7:0] ext_addr_4;
wire [7:0] ext_dout_QN;
wire [7:0] ext_addr_QN;
wire ext_io_wr_2 ;
wire ext_mem_wr_1_1 ;
wire ext_io_rd_1_1 ;
wire ext_mem_wr_QN ;
wire ext_io_wr_QN ;
wire ext_io_rd_QN ;
wire un6_export_i ;
wire N_51 ;
wire NN_1 ;
wire VCC ;
assign ext_io_wr_2 = (~Mico8_Instr_0 & iels_ie & ext_addr_cyc_int_Q) | 
   (~Mico8_Instr_0 & iels_ie & ext_addr_cyc_int_Q & ~addr_cyc) | (~Mico8_Instr_0 & 
   iels_ie & addr_cyc);
assign ext_mem_wr_1_1 = (~Mico8_Instr_0 & iels_ls & ext_addr_cyc_int_Q) | 
   (~Mico8_Instr_0 & iels_ls & ext_addr_cyc_int_Q & ~addr_cyc) | (~Mico8_Instr_0 & 
   iels_ls & addr_cyc);
assign ext_io_rd_1_1 = (ext_addr_cyc_int_Q & Mico8_Instr_0 & iels_ie) | 
   (ext_addr_cyc_int_Q & ~addr_cyc & Mico8_Instr_0 & iels_ie) | (addr_cyc & 
   Mico8_Instr_0 & iels_ie);
assign ext_addr_4[5] = (dout_rb[5] & Mico8_Instr_1) | (dout_rb[5] & Mico8_Instr_1 & 
   ~iels_ie) | (dout_rb[5] & ~iels_ls & ~iels_ie) | (dout_rb[5] & Mico8_Instr_1 & 
   iels_ls & ~iels_ie) | (dout_rb[5] & Mico8_Instr_1 & iels_ie);
assign ext_addr_4[6] = (dout_rb[6] & Mico8_Instr_1) | (dout_rb[6] & Mico8_Instr_1 & 
   ~iels_ie) | (dout_rb[6] & ~iels_ls & ~iels_ie) | (dout_rb[6] & Mico8_Instr_1 & 
   iels_ls & ~iels_ie) | (dout_rb[6] & Mico8_Instr_1 & iels_ie);
assign ext_addr_4[7] = (dout_rb[7] & Mico8_Instr_1) | (dout_rb[7] & Mico8_Instr_1 & 
   ~iels_ie) | (dout_rb[7] & ~iels_ls & ~iels_ie) | (dout_rb[7] & Mico8_Instr_1 & 
   iels_ls & ~iels_ie) | (dout_rb[7] & Mico8_Instr_1 & iels_ie);
// @4:99
  FD1S3AX ext_mem_wr_Z (
	.D(ext_mem_wr_1_1),
	.CK(MicoCLK),
	.Q(ext_mem_wr)
);
// @4:73
  FD1S3AX ext_io_wr_Z (
	.D(ext_io_wr_2),
	.CK(MicoCLK),
	.Q(Mico_WR_c)
);
// @4:73
  FD1S3AX ext_io_rd_Z (
	.D(ext_io_rd_1_1),
	.CK(MicoCLK),
	.Q(Mico_RD_c)
);
// @4:73
  FD1S3AX \ext_dout_Z[0]  (
	.D(dout_rd[0]),
	.CK(MicoCLK),
	.Q(MicoDOut[0])
);
// @4:73
  FD1S3AX \ext_dout_Z[1]  (
	.D(dout_rd[1]),
	.CK(MicoCLK),
	.Q(MicoDOut[1])
);
// @4:73
  FD1S3AX \ext_dout_Z[2]  (
	.D(dout_rd[2]),
	.CK(MicoCLK),
	.Q(MicoDOut[2])
);
// @4:73
  FD1S3AX \ext_dout_Z[3]  (
	.D(dout_rd[3]),
	.CK(MicoCLK),
	.Q(MicoDOut[3])
);
// @4:73
  FD1S3AX \ext_dout_Z[4]  (
	.D(dout_rd[4]),
	.CK(MicoCLK),
	.Q(MicoDOut[4])
);
// @4:73
  FD1S3AX \ext_dout_Z[5]  (
	.D(dout_rd[5]),
	.CK(MicoCLK),
	.Q(MicoDOut[5])
);
// @4:73
  FD1S3AX \ext_dout_Z[6]  (
	.D(dout_rd[6]),
	.CK(MicoCLK),
	.Q(MicoDOut[6])
);
// @4:73
  FD1S3AX \ext_dout_Z[7]  (
	.D(dout_rd[7]),
	.CK(MicoCLK),
	.Q(MicoDOut[7])
);
// @4:86
  FD1S3AX \ext_addr_Z[0]  (
	.D(ext_addr_4[0]),
	.CK(MicoCLK),
	.Q(MicoAddr[0])
);
// @4:86
  FD1S3AX \ext_addr_Z[1]  (
	.D(ext_addr_4[1]),
	.CK(MicoCLK),
	.Q(MicoAddr[1])
);
// @4:86