mico8.vm

Lattice 超精简8位软核CPU--Mico8

wire ie_flag ;
wire ie_flag_QN ;
wire un3_ext_addr_cyc_int_0_a2 ;
wire ext_addr_cyc_int_QN ;
wire N_18 ;
wire data_cyc_int_QN ;
wire carry_flag_int_1_1 ;
wire N_286_i ;
wire carry_flag_int_QN ;
wire N_280_i ;
wire br_enb_reg ;
wire br_enb_reg_QN ;
wire addr_cyc_int_QN ;
wire N_24_i ;
wire un1_stack_ptr_p4 ;
wire N_157 ;
wire zero_flag_1_i_a2_0_0 ;
wire intr_reg0_1_0_a2_4_tz_0_0 ;
wire N_110 ;
wire N_111 ;
wire N_112 ;
wire N_113 ;
wire N_114 ;
wire N_115 ;
wire N_116 ;
wire N_117 ;
wire prom_addr_i_0_m5_0_a2_0 ;
wire zero_flag_1_i_a2_0_5 ;
wire sp_we_1_i_o2_m8_i_1 ;
wire zero_flag_1_i_a2_0_6 ;
wire N_108 ;
wire intr_reg0_1_1_tz ;
wire N_145 ;
wire N_129 ;
wire intr_reg0_1_4 ;
wire pushed_zero ;
wire N_22 ;
wire N_24 ;
wire intr_reg0_1_0_a2_2 ;
wire N_125 ;
wire pushed_carry ;
wire un1_stack_ptr_axbxc3_1 ;
wire pc_int_cry_6 ;
wire pc_int_cry_7_0_COUT ;
wire pc_int_cry_4 ;
wire pc_int_cry_2 ;
wire pc_int_cry_0 ;
wire pc_int_cry_0_0_S0 ;
wire pc_int_cry_0_0_S1 ;
wire NN_1 ;
wire NN_2 ;
// @5:284
  FD1P3AX zero_flag_Z (
	.D(N_77),
	.SP(N_285_i),
	.CK(MicoCLK),
	.Q(zero_flag)
);
// @5:369
  FD1S3AX \stack_ptr_Z[0]  (
	.D(un1_stack_ptr_axb0),
	.CK(MicoCLK),
	.Q(stack_ptr[0])
);
// @5:369
  FD1S3AX \stack_ptr_Z[1]  (
	.D(un1_stack_ptr_axbxc1),
	.CK(MicoCLK),
	.Q(stack_ptr[1])
);
// @5:369
  FD1S3AX \stack_ptr_Z[2]  (
	.D(un1_stack_ptr_axbxc2),
	.CK(MicoCLK),
	.Q(stack_ptr[2])
);
// @5:369
  FD1S3AX \stack_ptr_Z[3]  (
	.D(un1_stack_ptr_axbxc3),
	.CK(MicoCLK),
	.Q(stack_ptr[3])
);
// @5:180
  FD1S3AX ret_reg_Z (
	.D(re),
	.CK(MicoCLK),
	.Q(ret_reg)
);
// @5:256
  FD1P3AX \pc_Z[0]  (
	.D(N_55_i),
	.SP(data_cyc_int),
	.CK(MicoCLK),
	.Q(pc[0])
);
// @5:256
  FD1P3AX \pc_Z[1]  (
	.D(N_57_i),
	.SP(data_cyc_int),
	.CK(MicoCLK),
	.Q(pc[1])
);
// @5:256
  FD1P3AX \pc_Z[2]  (
	.D(N_59_i),
	.SP(data_cyc_int),
	.CK(MicoCLK),
	.Q(pc[2])
);
// @5:256
  FD1P3AX \pc_Z[3]  (
	.D(N_61_i),
	.SP(data_cyc_int),
	.CK(MicoCLK),
	.Q(pc[3])
);
// @5:256
  FD1P3AX \pc_Z[4]  (
	.D(N_63_i),
	.SP(data_cyc_int),
	.CK(MicoCLK),
	.Q(pc[4])
);
// @5:256
  FD1P3AX \pc_Z[5]  (
	.D(N_65_i),
	.SP(data_cyc_int),
	.CK(MicoCLK),
	.Q(pc[5])
);
// @5:256
  FD1P3AX \pc_Z[6]  (
	.D(N_68_i),
	.SP(data_cyc_int),
	.CK(MicoCLK),
	.Q(pc[6])
);
// @5:256
  FD1P3AX \pc_Z[7]  (
	.D(N_70_i),
	.SP(data_cyc_int),
	.CK(MicoCLK),
	.Q(pc[7])
);
// @5:256
  FD1P3AX \pc_Z[8]  (
	.D(N_73_i),
	.SP(data_cyc_int),
	.CK(MicoCLK),
	.Q(pc[8])
);
// @5:193
  FD1P3AX intr_reg0_Z (
	.D(intr_reg0_1),
	.SP(addr_cyc),
	.CK(MicoCLK),
	.Q(intr_reg0)
);
// @5:323
  FD1P3AX intr_ack_int_Z (
	.D(g0_7),
	.SP(N_20),
	.CK(MicoCLK),
	.Q(INTAck_c)
);
// @5:308
  FD1P3AX ie_flag_Z (
	.D(clri_i),
	.SP(N_287_i),
	.CK(MicoCLK),
	.Q(ie_flag)
);
// @5:161
  FD1S3AX ext_addr_cyc_int_Z (
	.D(un3_ext_addr_cyc_int_0_a2),
	.CK(MicoCLK),
	.Q(ext_addr_cyc_int_Q)
);
// @5:161
  FD1S3AX data_cyc_int_Z (
	.D(N_18),
	.CK(MicoCLK),
	.Q(data_cyc_int)
);
// @5:268
  FD1P3AX carry_flag_int_Z (
	.D(carry_flag_int_1_1),
	.SP(N_286_i),
	.CK(MicoCLK),
	.Q(carry_flag)
);
// @5:206
  FD1P3AX br_enb_reg_Z (
	.D(N_280_i),
	.SP(addr_cyc),
	.CK(MicoCLK),
	.Q(br_enb_reg)
);
// @5:206
  FD1P3AX \addr_jmp_reg_Z[0]  (
	.D(Mico8_Instr_0),
	.SP(addr_cyc),
	.CK(MicoCLK),
	.Q(addr_jmp_reg[0])
);
// @5:206
  FD1P3AX \addr_jmp_reg_Z[1]  (
	.D(Mico8_Instr_1),
	.SP(addr_cyc),
	.CK(MicoCLK),
	.Q(addr_jmp_reg[1])
);
// @5:206
  FD1P3AX \addr_jmp_reg_Z[2]  (
	.D(Mico8_Instr_2),
	.SP(addr_cyc),
	.CK(MicoCLK),
	.Q(addr_jmp_reg[2])
);
// @5:206
  FD1P3AX \addr_jmp_reg_Z[3]  (
	.D(Mico8_Instr_3),
	.SP(addr_cyc),
	.CK(MicoCLK),
	.Q(addr_jmp_reg[3])
);
// @5:206
  FD1P3AX \addr_jmp_reg_Z[4]  (
	.D(Mico8_Instr_4),
	.SP(addr_cyc),
	.CK(MicoCLK),
	.Q(addr_jmp_reg[4])
);
// @5:206
  FD1P3AX \addr_jmp_reg_Z[5]  (
	.D(Mico8_Instr_5),
	.SP(addr_cyc),
	.CK(MicoCLK),
	.Q(addr_jmp_reg[5])
);
// @5:206
  FD1P3AX \addr_jmp_reg_Z[6]  (
	.D(Mico8_Instr_6),
	.SP(addr_cyc),
	.CK(MicoCLK),
	.Q(addr_jmp_reg[6])
);
// @5:206
  FD1P3AX \addr_jmp_reg_Z[7]  (
	.D(Mico8_Instr_7),
	.SP(addr_cyc),
	.CK(MicoCLK),
	.Q(addr_jmp_reg[7])
);
// @5:206
  FD1P3AX \addr_jmp_reg_Z[8]  (
	.D(Mico8_Instr_8),
	.SP(addr_cyc),
	.CK(MicoCLK),
	.Q(addr_jmp_reg[8])
);
// @5:161
  FD1S3AX addr_cyc_int_Z (
	.D(addr_cyc_int_1_1),
	.CK(MicoCLK),
	.Q(addr_cyc)
);
assign un1_stack_ptr_p4 = (N_24_i & un1_addr_cyc_int_i_a2_1[2] & stack_ptr[0]) | 
   (N_24_i & un1_addr_cyc_int_i_a2_1[2] & stack_ptr[0] & ~stack_ptr[1]) | 
   (N_24_i & stack_ptr[1]) | (N_24_i & ~stack_ptr[0] & stack_ptr[1]) | 
   (N_24_i & stack_ptr[0] & stack_ptr[1]) | (N_24_i & ~un1_addr_cyc_int_i_a2_1[2] & 
   stack_ptr[0] & stack_ptr[1]) | (un1_addr_cyc_int_i_a2_1[2] & stack_ptr[0] & 
   stack_ptr[1]);
assign N_157 = (br_enb_reg & data_cyc_int);
assign zero_flag_1_i_a2_0_0 = (~din_rd1[5] & ~din_rd1[6]);
assign intr_reg0_1_0_a2_4_tz_0_0 = (~Mico8_Instr_10) | (~Mico8_Instr_11) | 
   (~Mico8_Instr_10 & Mico8_Instr_11);
assign N_110 = (dout_stack[1] & pc_int[1]) | (pc_int[1] & ~ret_reg) | (dout_stack[1] & 
   ret_reg);
assign N_111 = (dout_stack[2] & pc_int[2]) | (pc_int[2] & ~ret_reg) | (dout_stack[2] & 
   ret_reg);
assign N_112 = (dout_stack[3] & pc_int[3]) | (pc_int[3] & ~ret_reg) | (dout_stack[3] & 
   ret_reg);
assign N_113 = (dout_stack[4] & pc_int[4]) | (pc_int[4] & ~ret_reg) | (dout_stack[4] & 
   ret_reg);
assign N_114 = (dout_stack[5] & pc_int[5]) | (pc_int[5] & ~ret_reg) | (dout_stack[5] & 
   ret_reg);
assign N_115 = (dout_stack[6] & pc_int[6]) | (pc_int[6] & ~ret_reg) | (dout_stack[6] & 
   ret_reg);
assign N_116 = (dout_stack[7] & pc_int[7]) | (pc_int[7] & ~ret_reg) | (dout_stack[7] & 
   ret_reg);
assign N_117 = (dout_stack[8] & pc_int[8]) | (pc_int[8] & ~ret_reg) | (dout_stack[8] & 
   ret_reg);
assign N_20 = (iret & data_cyc_int) | (iret & ~g0_7 & data_cyc_int) | (g0_7 & 
   data_cyc_int);
assign prom_addr_i_0_m5_0_a2_0 = (intr_reg0 & ~INTAck_c & data_cyc_int);
assign zero_flag_1_i_a2_0_5 = (~din_rd1[0] & ~din_rd1[1] & ~din_rd1[2] & 
   ~din_rd1[7]);
assign sp_we_1_i_o2_N_14_i = (carry_flag & zero_flag & ~Mico8_Instr_10) | 
   (~carry_flag & ~zero_flag & Mico8_Instr_10) | (zero_flag & ~Mico8_Instr_10 & 
   ~Mico8_Instr_11) | (~zero_flag & Mico8_Instr_10 & ~Mico8_Instr_11) | 
   (carry_flag & ~Mico8_Instr_10 & Mico8_Instr_11) | (~carry_flag & Mico8_Instr_10 & 
   Mico8_Instr_11);
assign pc_int[0] = (addr_jmp_reg[0] & ~pc[0]) | (~br_enb_reg & ~pc[0]) | 
   (addr_jmp_reg[0] & br_enb_reg & ~pc[0]) | (~pc[0] & ~data_cyc_int) | 
   (addr_jmp_reg[0] & ~pc[0] & data_cyc_int) | (~br_enb_reg & ~pc[0] & 
   data_cyc_int) | (addr_jmp_reg[0] & br_enb_reg & ~pc[0] & data_cyc_int) | 
   (~addr_jmp_reg[0] & br_enb_reg & pc[0] & data_cyc_int);
assign sp_we_1_i_o2_m8_i_1 = (~instr_l1_3) | (~Mico8_Instr_13) | (~instr_l1_3 & 
   Mico8_Instr_13) | (~Mico8_Instr_14) | (~instr_l1_3 & Mico8_Instr_14) | 
   (~Mico8_Instr_13 & Mico8_Instr_14) | (~instr_l1_3 & Mico8_Instr_13 & 
   Mico8_Instr_14) | (~instr_l1_3 & ~Mico8_Instr_15) | (~Mico8_Instr_13 & 
   ~Mico8_Instr_15) | (~instr_l1_3 & Mico8_Instr_13 & ~Mico8_Instr_15) | 
   (~Mico8_Instr_14 & ~Mico8_Instr_15) | (~instr_l1_3 & Mico8_Instr_14 & 
   ~Mico8_Instr_15) | (~Mico8_Instr_13 & Mico8_Instr_14 & ~Mico8_Instr_15) | 
   (~instr_l1_3 & Mico8_Instr_13 & Mico8_Instr_14 & ~Mico8_Instr_15) | 
   (Mico8_Instr_15);
assign zero_flag_1_i_a2_0_6 = (~din_rd1[3] & ~din_rd1[4] & zero_flag_1_i_a2_0_0 & 
   data_cyc_int);
assign N_57_i = (~g0_7 & dout_stack[1] & pc_int[1]) | (~g0_7 & pc_int[1] & 
   ~ret_reg) | (~g0_7 & dout_stack[1] & ret_reg);
assign N_59_i = (~g0_7 & dout_stack[2] & pc_int[2]) | (~g0_7 & pc_int[2] & 
   ~ret_reg) | (~g0_7 & dout_stack[2] & ret_reg);
assign N_61_i = (~g0_7 & dout_stack[3] & pc_int[3]) | (~g0_7 & pc_int[3] & 
   ~ret_reg) | (~g0_7 & dout_stack[3] & ret_reg);
assign N_63_i = (~g0_7 & dout_stack[4] & pc_int[4]) | (~g0_7 & pc_int[4] & 
   ~ret_reg) | (~g0_7 & dout_stack[4] & ret_reg);
assign N_65_i = (~g0_7 & dout_stack[5] & pc_int[5]) | (~g0_7 & pc_int[5] & 
   ~ret_reg) | (~g0_7 & dout_stack[5] & ret_reg);
assign N_68_i = (~g0_7 & dout_stack[6] & pc_int[6]) | (~g0_7 & pc_int[6] & 
   ~ret_reg) | (~g0_7 & dout_stack[6] & ret_reg);
assign N_70_i = (~g0_7 & dout_stack[7] & pc_int[7]) | (~g0_7 & pc_int[7] & 
   ~ret_reg) | (~g0_7 & dout_stack[7] & ret_reg);
assign N_73_i = (~g0_7 & dout_stack[8] & pc_int[8]) | (~g0_7 & pc_int[8] & 
   ~ret_reg) | (~g0_7 & dout_stack[8] & ret_reg);
assign N_302_i = (N_110 & ~g0_7) | (N_110 & ~data_cyc_int) | (N_110 & ~g0_7 & 
   data_cyc_int);
assign N_304_i = (N_112 & ~g0_7) | (N_112 & ~data_cyc_int) | (N_112 & ~g0_7 & 
   data_cyc_int);
assign N_305_i = (N_113 & ~g0_7) | (N_113 & ~data_cyc_int) | (N_113 & ~g0_7 & 
   data_cyc_int);
assign N_306_i = (N_114 & ~g0_7) | (N_114 & ~data_cyc_int) | (N_114 & ~g0_7 & 
   data_cyc_int);
assign N_307_i = (N_115 & ~g0_7) | (N_115 & ~data_cyc_int) | (N_115 & ~g0_7 & 
   data_cyc_int);
assign N_51_i = (N_116 & ~g0_7) | (N_116 & ~data_cyc_int) | (N_116 & ~g0_7 & 
   data_cyc_int);
assign N_53_i = (N_117 & ~g0_7) | (N_117 & ~data_cyc_int) | (N_117 & ~g0_7 & 
   data_cyc_int);
assign un3_ext_addr_cyc_int_0_a2 = (addr_cyc & instr_l1_3 & instr_l2_3 & 
   ~Mico8_Instr_13);
assign N_108 = (dout_stack[0] & pc_int[0]) | (pc_int[0] & ~ret_reg) | (dout_stack[0] & 
   ret_reg);
assign N_18 = (addr_cyc & ~iels) | (addr_cyc & ~iels & ~ext_addr_cyc_int_Q) | 
   (ext_addr_cyc_int_Q);
assign intr_reg0_1_1_tz = (~ca0 & ~un1_br0) | (~ca0 & ~un1_br0 & ~Mico8_Instr_12) | 
   (~ca0 & Mico8_Instr_12);
assign N_145 = (zero_flag_1_i_a2_0_5 & zero_flag_1_i_a2_0_6 & ~update_z_0) | 
   (zero_flag_1_i_a2_0_5 & zero_flag_1_i_a2_0_6 & ~update_z_0 & ~update_z_1) | 
   (zero_flag_1_i_a2_0_5 & zero_flag_1_i_a2_0_6 & update_z_1);
assign N_129 = (addr_cyc & sp_we_1_i_o2_N_14_i & ~sp_we_1_i_o2_m8_i_1) | 
   (addr_cyc & sp_we_1_i_o2_N_14_i & ~sp_we_1_i_o2_m8_i_1 & ~Mico8_Instr_12) | 
   (addr_cyc & ~sp_we_1_i_o2_m8_i_1 & Mico8_Instr_12);
assign N_285_i = (iret) | (~update_z_0) | (iret & update_z_0) | (iret & 
   ~update_z_1) | (~update_z_0 & ~update_z_1) | (iret & update_z_0 & ~update_z_1) | 
   (update_z_1);
assign N_287_i = (sc & ~Mico8_Instr_1 & Mico8_Instr_2);
assign intr_reg0_1_4 = (intr_reg0_1_0_a2_4_tz_0_0) | (intr_reg0_1_0_a2_4_tz_0_0 & 
   ~un1_br0) | (~ca0 & ~un1_br0) | (intr_reg0_1_0_a2_4_tz_0_0 & ca0 & 
   ~un1_br0) | (intr_reg0_1_0_a2_4_tz_0_0 & un1_br0) | (intr_reg0_1_0_a2_4_tz_0_0 & 
   ~Mico8_Instr_12) | (intr_reg0_1_0_a2_4_tz_0_0 & ~un1_br0 & ~Mico8_Instr_12) | 
   (~ca0 & ~un1_br0 & ~Mico8_Instr_12) | (intr_reg0_1_0_a2_4_tz_0_0 & 
   ca0 & ~un1_br0 & ~Mico8_Instr_12) | (intr_reg0_1_0_a2_4_tz_0_0 & un1_br0 & 
   ~Mico8_Instr_12) | (intr_reg0_1_0_a2_4_tz_0_0 & Mico8_Instr_12) | (~ca0 & 
   Mico8_Instr_12) | (intr_reg0_1_0_a2_4_tz_0_0 & ca0 & Mico8_Instr_12);
assign N_77 = (setz) | (setz & ~N_145) | (N_145) | (setz & ~pushed_zero) | 
   (setz & ~N_145 & ~pushed_zero) | (N_145 & ~pushed_zero) | (iret & pushed_zero) | 
   (iret & ~setz & pushed_zero) | (setz & pushed_zero) | (iret & ~N_145 &