mico8.tw1

Lattice 超精简8位软核CPU--Mico8

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Lattice TRACE Report, Version ispLever_v70_SP2_Build (24)
Fri Mar 14 11:43:24 2008

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -o checkpnt.twr mico8_map.ncd mico8.prf 
Design file:     mico8_map.ncd
Preference file: mico8.prf
Device,speed:    LFE2-6E,7
Report level:    verbose report, limited to 1 item per preference
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BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
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Derating parameters
-------------------
Temperature:   25 C
Voltage:    1.200 V  (Preference `VCC_DERATE` is ignored)



================================================================================
Preference: FREQUENCY NET "CLK_IN_c" 25.000000 MHz ;
            0 items scored, 0 timing errors detected.
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================================================================================
Preference: FREQUENCY NET "MicoCLK" 150.000000 MHz PAR_ADJ 75.000000 ;
            4096 items scored, 0 timing errors detected.
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Passed:  The following path meets requirements by 3.012ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         DP16KB     Port           I61/ProgPRom_0_0_0(ASIC)  (from MicoCLK +)
   Destination:    FF         Data in        I78/u1_isp8/u1_isp8_flow_cntl/carry_flag_int$r43  (to MicoCLK +)

   Delay:               3.602ns  (100.0% logic, 0.0% route), 9 logic levels.

 Constraint Details:

       3.602ns physical path delay I61/ProgPRom_0_0_0 to I78/u1_isp8/SLICE_173 meets
       6.666ns delay constraint less
       0.052ns DIN_SET requirement (totaling 6.614ns) by 3.012ns

 Physical Path Details:

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     2.148 Rom_0_0_0.CLKA to om_0_0_0.DOA15 I61/ProgPRom_0_0_0 (from MicoCLK)
ROUTE        27   e 0.000 om_0_0_0.DOA15 to u/SLICE_303.A1 Mico8_Instr_15
CTOOFX_DEL  ---     0.263 u/SLICE_303.A1 to SLICE_303.OFX0 I78/u1_isp8/u1_isp8_alu/SLICE_303
ROUTE         3   e 0.000 SLICE_303.OFX0 to 8/SLICE_293.C1 I78/u1_isp8/u1_isp8_alu/N_144
CTOOFX_DEL  ---     0.263 8/SLICE_293.C1 to SLICE_293.OFX0 I78/u1_isp8/u1_isp8_alu/u1_addsub8/SLICE_293
ROUTE         1   e 0.000 SLICE_293.OFX0 to b8/SLICE_43.B0 I78/u1_isp8/u1_isp8_alu/u1_addsub8/ci_k
C0TOFCO_DE  ---     0.336 b8/SLICE_43.B0 to 8/SLICE_43.FCO I78/u1_isp8/u1_isp8_alu/u1_addsub8/SLICE_43
ROUTE         1   e 0.000 8/SLICE_43.FCO to 8/SLICE_44.FCI I78/u1_isp8/u1_isp8_alu/u1_addsub8/co0
FCITOFCO_D  ---     0.064 8/SLICE_44.FCI to 8/SLICE_44.FCO I78/u1_isp8/SLICE_44
ROUTE         1   e 0.000 8/SLICE_44.FCO to 8/SLICE_45.FCI I78/u1_isp8/u1_isp8_alu/u1_addsub8/co1
FCITOFCO_D  ---     0.064 8/SLICE_45.FCI to 8/SLICE_45.FCO I78/u1_isp8/SLICE_45
ROUTE         1   e 0.000 8/SLICE_45.FCO to 8/SLICE_46.FCI I78/u1_isp8/u1_isp8_alu/u1_addsub8/co2
FCITOFCO_D  ---     0.064 8/SLICE_46.FCI to 8/SLICE_46.FCO I78/u1_isp8/SLICE_46
ROUTE         1   e 0.000 8/SLICE_46.FCO to 8/SLICE_42.FCI I78/u1_isp8/u1_isp8_alu/u1_addsub8/co3
FCITOF1_DE  ---     0.245 8/SLICE_42.FCI to b8/SLICE_42.F1 I78/u1_isp8/u1_isp8_alu/u1_addsub8/SLICE_42
ROUTE         1   e 0.000 b8/SLICE_42.F1 to 8/SLICE_173.C0 I78/u1_isp8/u1_isp8_alu/carry_add_int
CTOF_DEL    ---     0.155 8/SLICE_173.C0 to 8/SLICE_173.F0 I78/u1_isp8/SLICE_173
ROUTE         1   e 0.000 8/SLICE_173.F0 to /SLICE_173.DI0 I78/u1_isp8/N_140$n87 (to MicoCLK)
                  --------
                    3.602   (100.0% logic, 0.0% route), 9 logic levels.

Report:  273.673MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "X2CLK_c" 100.000000 MHz ;
            0 items scored, 0 timing errors detected.
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Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "CLK_IN_c" 25.000000 MHz  |             |             |
;                                       |            -|            -|     0
                                        |             |             |
FREQUENCY NET "MicoCLK" 150.000000 MHz  |             |             |
PAR_ADJ 75.000000 ;                     |  150.000 MHz|  273.673 MHz|     9
                                        |             |             |
FREQUENCY NET "X2CLK_c" 100.000000 MHz  |             |             |
;                                       |            -|            -|     0
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Timing summary:
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 9704 paths, 233 nets, and 3001 connections (90.1% coverage)

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