📄 mico8.twr
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Lattice TRACE Report, Version ispLever_v70_SP2_Build (24)
Fri Mar 14 11:45:14 2008
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce.exe -v 1 -o mico8.twr mico8.ncd mico8.prf
Design file: mico8.ncd
Preference file: mico8.prf
Device,speed: LFE2-6E,7
Report level: verbose report, limited to 1 item per preference
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BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Temperature: 25 C
Voltage: 1.200 V (Preference `VCC_DERATE` is ignored)
================================================================================
Preference: FREQUENCY NET "CLK_IN_c" 25.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "MicoCLK" 150.000000 MHz PAR_ADJ 75.000000 ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.400ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP16KB Port I61/ProgPRom_0_0_0(ASIC) (from MicoCLK +)
Destination: FF Data in I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/RAM0 (to I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/WCK_INT +)
FF I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/RAM0
Delay: 6.334ns (43.9% logic, 56.1% route), 6 logic levels.
Constraint Details:
6.334ns physical path delay I61/ProgPRom_0_0_0 to I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/SLICE_75 meets
6.666ns delay constraint less
0.080ns skew and
0.000ns feedback compensation and
-0.148ns WD_SET requirement (totaling 6.734ns) by 0.400ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 2.148 BR_R19C20.CLKA to R_R19C20.DOA14 I61/ProgPRom_0_0_0 (from MicoCLK)
ROUTE 22 0.468 R_R19C20.DOA14 to R20C22A.C0 Mico8_Instr_14
CTOF_DEL --- 0.155 R20C22A.C0 to R20C22A.F0 I78/u1_isp8/SLICE_383
ROUTE 3 0.752 R20C22A.F0 to R20C22C.M0 I78/u1_isp8/instr_l2_3
MTOOFX_DEL --- 0.162 R20C22C.M0 to R20C22C.OFX0 I78/u1_isp8/SLICE_183
ROUTE 24 0.763 R20C22C.OFX0 to R22C19C.D1 I78/u1_isp8/iels_ls$n147
CTOF_DEL --- 0.155 R22C19C.D1 to R22C19C.F1 I78/u1_isp8/SLICE_277
ROUTE 1 0.765 R22C19C.F1 to R22C19B.M0 I78/u1_isp8/N_284_3
MTOOFX_DEL --- 0.162 R22C19B.M0 to R22C19B.OFX0 I78/u1_isp8/SLICE_312
ROUTE 4 0.804 R22C19B.OFX0 to R20C17B.B1 I78/u1_isp8/din_rd_1
ZERO_DEL --- 0.000 R20C17B.B1 to R20C17B.WDO1 I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/SLICE_74
ROUTE 1 0.000 R20C17B.WDO1 to R20C17A.WD1 I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/WD1_INT (to I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/WCK_INT)
--------
6.334 (43.9% logic, 56.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.459 14.PAD to 14.PADDI CLK_IN
ROUTE 1 0.779 14.PADDI to PLL_R19C3.CLKI CLK_IN_c
CLK2SEC_DE --- 0.000 PLL_R19C3.CLKI to LL_R19C3.CLKOK I47/PLLDInst_0
ROUTE 258 0.865 LL_R19C3.CLKOK to BR_R19C20.CLKA MicoCLK
--------
2.103 (21.8% logic, 78.2% route), 2 logic levels.
Destination Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.459 14.PAD to 14.PADDI CLK_IN
ROUTE 1 0.779 14.PADDI to PLL_R19C3.CLKI CLK_IN_c
CLK2SEC_DE --- 0.000 PLL_R19C3.CLKI to LL_R19C3.CLKOK I47/PLLDInst_0
ROUTE 258 0.785 LL_R19C3.CLKOK to R20C17B.CLK MicoCLK
ZERO_DEL --- 0.000 R20C17B.CLK to R20C17B.WCKO I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/SLICE_74
ROUTE 2 0.000 R20C17B.WCKO to R20C17A.WCK I78/u1_isp8/GEN_REG_32_u2_isp8_rfmem/mem_0_1/WCK_INT
--------
2.023 (22.7% logic, 77.3% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB_DEL --- 0.000 LL_R19C3.CLKFB to R19C3.CLKINTFB I47/PLLDInst_0
ROUTE 1 0.000 R19C3.CLKINTFB to LL_R19C3.CLKFB I47/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
PLL_R19C3.CLKINTFB attributes:
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB_DEL --- 0.000 LL_R19C3.CLKFB to R19C3.CLKINTFB I47/PLLDInst_0
ROUTE 1 0.000 R19C3.CLKINTFB to LL_R19C3.CLKFB I47/CLKFB_t
--------
0.000 (0.0% logic, 0.0% route), 1 logic levels.
PLL_R19C3.CLKINTFB attributes:
Report: 159.591MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "X2CLK_c" 100.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "CLK_IN_c" 25.000000 MHz | | |
; | -| -| 0
| | |
FREQUENCY NET "MicoCLK" 150.000000 MHz | | |
PAR_ADJ 75.000000 ; | 150.000 MHz| 159.591 MHz| 6
| | |
FREQUENCY NET "X2CLK_c" 100.000000 MHz | | |
; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Timing summary:
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 9704 paths, 233 nets, and 3034 connections (91.1% coverage)
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