progprom.vhd

Lattice 超精简8位软核CPU--Mico8

    attribute DATA_WIDTH_B : string; 
    attribute DATA_WIDTH_A : string; 
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    attribute CSDECODE_B of ProgPRom_0_0_0 : label is "0b000";
    attribute CSDECODE_A of ProgPRom_0_0_0 : label is "0b000";
    attribute WRITEMODE_B of ProgPRom_0_0_0 : label is "NORMAL";
    attribute WRITEMODE_A of ProgPRom_0_0_0 : label is "NORMAL";
    attribute GSR of ProgPRom_0_0_0 : label is "DISABLED";
    attribute RESETMODE of ProgPRom_0_0_0 : label is "ASYNC";
    attribute REGMODE_B of ProgPRom_0_0_0 : label is "NOREG";
    attribute REGMODE_A of ProgPRom_0_0_0 : label is "NOREG";
    attribute DATA_WIDTH_B of ProgPRom_0_0_0 : label is "18";
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begin
    -- component instantiation statements
    scuba_vhi_inst: VHI
        port map (Z=>scuba_vhi);

    scuba_vlo_inst: VLO
        port map (Z=>scuba_vlo);

    ProgPRom_0_0_0: DP16KB
        -- synopsys translate_off
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        INITVAL_00=> "0x222FE370823C2483C238282103704337030370173701237013370142C00512601122FE121013309E", 
        CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
        WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", 
        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  18, 
        DATA_WIDTH_A=>  18)
        -- synopsys translate_on
        port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, 
            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
            ADA3=>scuba_vlo, ADA4=>Address(0), ADA5=>Address(1), 
            ADA6=>Address(2), ADA7=>Address(3), ADA8=>Address(4), 
            ADA9=>Address(5), ADA10=>Address(6), ADA11=>Address(7), 
            ADA12=>Address(8), ADA13=>scuba_vlo, CEA=>OutClockEn, 
            CLKA=>OutClock, WEA=>scuba_vlo, CSA0=>scuba_vlo, 
            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
            ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo, 
            ADB3=>scuba_vlo, ADB4=>Address(0), ADB5=>Address(1), 
            ADB6=>Address(2), ADB7=>Address(3), ADB8=>Address(4), 
            ADB9=>Address(5), ADB10=>Address(6), ADB11=>Address(7), 
            ADB12=>Address(8), ADB13=>scuba_vhi, CEB=>OutClockEn, 
            CLKB=>OutClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, 
            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>Q(0), 
            DOA1=>Q(1), DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), 
            DOA6=>Q(6), DOA7=>Q(7), DOA8=>Q(8), DOA9=>Q(9), DOA10=>Q(10), 
            DOA11=>Q(11), DOA12=>Q(12), DOA13=>Q(13), DOA14=>Q(14), 
            DOA15=>Q(15), DOA16=>Q(16), DOA17=>Q(17), DOB0=>open, 
            DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, 
            DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, 
            DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, 
            DOB15=>open, DOB16=>open, DOB17=>open);

end Structure;

-- synopsys translate_off
library ecp2;
configuration Structure_CON of ProgPRom is
    for Structure
        for all:VHI use entity ecp2.VHI(V); end for;
        for all:VLO use entity ecp2.VLO(V); end for;
        for all:DP16KB use entity ecp2.DP16KB(V); end for;
    end for;
end Structure_CON;

-- synopsys translate_on