serout_m8.vhd

Lattice 超精简8位软核CPU--Mico8

-----------------------------------------------------------------------
-- Serout_M8.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--           
--                     Lattice Semiconductor Corporation
--                     5555 NE Moore Court
--                     Hillsboro, OR 97214
--                     U.S.A
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--                     TEL: 1-800-Lattice (USA and Canada)
--                          408-826-6000 (other locations)
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--                     web: http://www.latticesemi.com/
--                     email: [e-mail]
--
-- --------------------------------------------------------------------
--
-- This is a Mico8 peripheral that sends 8bit serial data
-- Address map:
-- 00001001: Data register
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
--   Ver  :| Author            :| Mod. Date :| Changes Made:
--   V1.1 :| G.M.              :| 13/03/08  :| initialised Dserdata, zWR
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity serout_M8 is
port (
	Clk : in std_logic;
	Reset : in std_logic;
	WR : in std_logic;
	Addr: in std_logic_vector(7 downto 0);
	Mico8_Data : in std_logic_vector (7 downto 0);
	Valid : out std_logic;
	Ser_Out : out std_logic
	);
end serout_M8;

architecture behave of serout_M8 is

signal zWR : std_logic;
constant seraddress: std_logic_vector (7 downto 0) := "00001001";
signal shift_cnt: natural range 0 to 8;
signal dserdata: std_logic_vector (7 downto 0);

attribute pgroup : string;
attribute pgroup of behave : architecture is "Serout";

begin

serializer: process (clk, reset, WR)
begin
	if reset = '1' then
		shift_cnt <= 0;
		ser_out <= '0';
		valid <= '0';
		dserdata <= (others => '0');
		zWR <= WR;
	elsif clk'event and clk = '1' then
		zWR <= WR;
		if (zWR /= WR) and (WR = '0') then
			if Addr = seraddress then
				dserdata(7 downto 0) <= Mico8_Data(7 downto 0);
				shift_cnt <= 8;
			else
				dserdata(7 downto 0) <= dserdata(7 downto 0);
			end if;
		elsif shift_cnt /= 0 then
			valid <= '1';
			ser_out <= dserdata(shift_cnt - 1);
			shift_cnt <= shift_cnt - 1;
		else
			valid <= '0';
			ser_out <= '0';	 
		end if;
	end if;
end process;

	
end behave;