isp8_idec.vhd

Lattice 超精简8位软核CPU--Mico8

------------------------------------------------------------------------------
-- 
--  Name:   isp8_idec.vhd
-- 
--  Description:  Instruction decode logic
-- 
--  $Revision: 1.2 $
--  
------------------------------------------------------------------------------
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
------------------------------------------------------------------------------
--
--    Lattice Semiconductor Corporation
--    5555 NE Moore Court
--    Hillsboro, OR 97124
--    U.S.A
--
--    TEL: 1-800-Lattice (USA and Canada)
--    408-826-6000 (other locations)
--
--    web: http://www.latticesemi.com/
--    email: [e-mail]
-- 
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity isp8_idec is
    generic(PROM_AW : natural := 10);
    port(instr     : in  std_logic_vector(17 downto 0);
         imi_instr : out std_logic;
         sub       : out std_logic;
         subc      : out std_logic;
         add       : out std_logic;
         addc      : out std_logic;
         mov       : out std_logic;
         andr      : out std_logic;
         orr       : out std_logic;
         xorr      : out std_logic;
         cmp       : out std_logic;
         test      : out std_logic;
         ror1      : out std_logic;
         rorc      : out std_logic;
         rol1      : out std_logic;
         rolc      : out std_logic;
         clrc      : out std_logic;
         setc      : out std_logic;
         clrz      : out std_logic;
         setz      : out std_logic;
         clri      : out std_logic;
         seti      : out std_logic;
         bz        : out std_logic;
         bnz       : out std_logic;
         bc        : out std_logic;
         bnc       : out std_logic;
         b         : out std_logic;
         callz     : out std_logic;
         callnz    : out std_logic;
         callc     : out std_logic;
         callnc    : out std_logic;
         call      : out std_logic;
         ret       : out std_logic;
         iret      : out std_logic;
         export    : out std_logic;
         exporti   : out std_logic;
         import    : out std_logic;
         importi   : out std_logic;
         ssp       : out std_logic;
         lsp       : out std_logic;
         sspi      : out std_logic;
         lspi      : out std_logic;
         addr_rb   : out std_logic_vector(4 downto 0);
         addr_rd   : out std_logic_vector(4 downto 0);
         imi_data  : out std_logic_vector(7 downto 0);
         addr_jmp  : out std_logic_vector((PROM_AW - 1) downto 0);
         update_c  : out std_logic;
         update_z  : out std_logic);
end isp8_idec;


architecture behave of isp8_idec is

    signal instr_l1_0, instr_l1_1, instr_l1_2, instr_l1_3 : std_logic;
    signal instr_l2_0, instr_l2_1, instr_l2_2, instr_l2_3 : std_logic;
    signal instr_l3_0, instr_l3_1 : std_logic;
    signal instr_l4_0, instr_l4_1 : std_logic;
    signal instr_l5_0, instr_l5_1, instr_l5_2, instr_l5_3 : std_logic;
    signal instr_l6_0, instr_l6_1 : std_logic;
    signal instr_l7_0, instr_l7_1, instr_l7_2, instr_l7_3 : std_logic;

    signal ro : std_logic;
    signal sc : std_logic;
    signal br0, br1 : std_logic;
    signal ca0, ca1 : std_logic;
    signal re : std_logic;
    signal iels : std_logic;
    signal iels_ie : std_logic;
    signal iels_ls : std_logic;

begin

-- Level 1 decodes of bits [17:16]
    instr_l1_0 <= (NOT(instr(17)) AND NOT(instr(16)));
    instr_l1_1 <= (NOT(instr(17)) AND instr(16));
    instr_l1_2 <= (instr(17) AND NOT(instr(16)));
    instr_l1_3 <= (instr(17) AND instr(16));

-- Level 2 decodes of bits [15:14]
    instr_l2_0 <= (NOT(instr(15)) AND NOT(instr(14)));
    instr_l2_1 <= (NOT(instr(15)) AND instr(14));
    instr_l2_2 <= (instr(15) AND NOT(instr(14)));
    instr_l2_3 <= (instr(15) AND instr(14));

-- Level 3 decodes of bits [13]
    instr_l3_0 <= NOT(instr(13));
    instr_l3_1 <= instr(13);

-- Level 4 decodes of bits [12]
    instr_l4_0 <= NOT(instr(12));
    instr_l4_1 <= instr(12);

-- Level 5 decodes of bits [11:10]
    instr_l5_0 <= (NOT(instr(11)) AND NOT(instr(10)));
    instr_l5_1 <= (NOT(instr(11)) AND instr(10));
    instr_l5_2 <= (instr(11) AND NOT(instr(10)));
    instr_l5_3 <= (instr(11) AND instr(10));

-- Level 6 decodes of bits [2]
    instr_l6_0 <= NOT(instr(2));
    instr_l6_1 <= instr(2);

-- Level 7 decodes of bits [1:0]
    instr_l7_0 <= (NOT(instr(1)) AND NOT(instr(0)));
    instr_l7_1 <= (NOT(instr(1)) AND instr(0));
    instr_l7_2 <= (instr(1) AND NOT(instr(0)));
    instr_l7_3 <= (instr(1) AND instr(0));

-- Immediate operand instruction decode
    imi_instr <= instr_l3_1;

-- Decodes for sub* instructions
    sub   <= instr_l1_0 AND instr_l2_0 ;
    subc  <= instr_l1_0 AND instr_l2_1 ;

-- Decodes for add* instructions
    add   <= instr_l1_0 AND instr_l2_2 ;
    addc  <= instr_l1_0 AND instr_l2_3 ;

-- Decodes for mov* instructions
    mov <= instr_l1_1 AND instr_l2_0 ;

-- Decodes for logic* instructions
    andr <= instr_l1_1 AND instr_l2_1 ;
    orr  <= instr_l1_1 AND instr_l2_2 ;
    xorr <= instr_l1_1 AND instr_l2_3 ;

-- Decodes for compare/test instructions
    cmp  <= instr_l1_2 AND instr_l2_0 ;
    test <= instr_l1_2 AND instr_l2_1 ;

-- Decodes for rotate instructions
    ro   <= instr_l1_2 AND instr_l2_2 AND instr_l3_0 ;
    ror1 <= ro AND instr_l7_0 ;
    rorc <= ro AND instr_l7_2 ;
    rol1 <= ro AND instr_l7_1 ;
    rolc <= ro AND instr_l7_3 ;

-- Decodes for set/clear instructions
    sc   <= instr_l1_2 AND instr_l2_3 ;
    clrc <= sc AND instr_l6_0 AND instr_l7_0 ;
    setc <= sc AND instr_l6_0 AND instr_l7_1 ;
    clrz <= sc AND instr_l6_0 AND instr_l7_2 ;
    setz <= sc AND instr_l6_0 AND instr_l7_3 ;
    clri <= sc AND instr_l6_1 AND instr_l7_0 ;
    seti <= sc AND instr_l6_1 AND instr_l7_1 ;

-- Decodes for branch instructions
    br0  <= instr_l1_3 AND instr_l2_0 AND instr_l3_1 AND instr_l4_0 ;
    br1  <= instr_l1_3 AND instr_l2_0 AND instr_l3_1 AND instr_l4_1 ;
    bz   <= br0 AND instr_l5_0 ;
    bnz  <= br0 AND instr_l5_1 ;
    bc   <= br0 AND instr_l5_2 ;
    bnc  <= br0 AND instr_l5_3 ;
    b    <= br1 ;

-- Decodes for call instructions
    ca0    <= instr_l1_3 AND instr_l2_1 AND instr_l3_1 AND instr_l4_0 ;
    ca1    <= instr_l1_3 AND instr_l2_1 AND instr_l3_1 AND instr_l4_1 ;
    callz  <= ca0 AND instr_l5_0 ;
    callnz <= ca0 AND instr_l5_1 ;
    callc  <= ca0 AND instr_l5_2 ;
    callnc <= ca0 AND instr_l5_3 ;
    call   <= ca1 ;

-- Decodes for return instructions
    re   <= instr_l1_3 AND instr_l2_2 ;
    ret  <= re AND instr_l4_0 ;
    iret <= re AND instr_l4_1 ;

-- Decodes for import/export instructions
    iels    <= instr_l1_3 AND instr_l2_3 AND instr_l3_0 ;
    iels_ie <= iels AND instr_l6_0 ;
    export  <= iels_ie AND instr_l7_0 ;
    import  <= iels_ie AND instr_l7_1 ;
    exporti <= iels_ie AND instr_l7_2 ;
    importi <= iels_ie AND instr_l7_3 ;

-- Decodes for load/store instructions
    iels_ls <= iels AND instr_l6_1 ;
    ssp     <= iels_ls AND instr_l7_0 ;
    lsp     <= iels_ls AND instr_l7_1 ;
    sspi    <= iels_ls AND instr_l7_2 ;
    lspi    <= iels_ls AND instr_l7_3 ;

-- Rd address
    addr_rd <= instr(12 downto 8) ;

-- Rb address
    addr_rb <= instr(7 downto 3) ;

-- Constant data from immediate instructions
    imi_data<= instr(7 downto 0) ;

-- Label from branch/call instructions
    JMP_INST_13: if (PROM_AW > 12) generate
       signal sign_extend1 : std_logic_vector(PROM_AW-13 downto 0);
       signal sign_extend2 : std_logic_vector(PROM_AW-11 downto 0);
       begin
          A1: for loopVar1 in 0 to PROM_AW-13 generate
             sign_extend1(loopVar1) <= instr(11);
          end generate A1;
          A2: for loopVar2 in 0 to PROM_AW-11 generate
             sign_extend2(loopVar2) <= instr(9);
          end generate A2;
       addr_jmp <= (sign_extend1 & instr(11 downto 0)) when ((ca1 = '1') or (br1 = '1')) else
                   (sign_extend2 & instr(9 downto 0));
       end generate;

    JMP_INST_11_12: if ((PROM_AW > 10) and (PROM_AW <= 12)) = true generate
       signal sign_extend2 : std_logic_vector(PROM_AW-11 downto 0);
       begin
          A1: for loopVar2 in 0 to PROM_AW-11 generate
             sign_extend2(loopVar2) <= instr(9);
          end generate A1;
       addr_jmp <= instr((PROM_AW - 1) downto 0) when ((ca1 = '1') or (br1 = '1')) else
                   (sign_extend2 & instr(9 downto 0));
    end generate JMP_INST_11_12;

    JMP_INST_10: if (PROM_AW <= 10) generate
       addr_jmp <= instr((PROM_AW - 1) downto 0);
    end generate JMP_INST_10;

-- Enable Carry/Zero Flag update
    update_c <=  (instr_l1_0  OR (instr_l1_2 AND NOT(instr_l2_3) AND instr(1)) OR (instr_l1_2 AND instr_l2_0)) ;
    update_z <=  (instr_l1_0  OR (instr_l1_1 AND NOT(instr_l2_0)) OR 
                                  (instr_l1_2 AND NOT(instr_l2_3 AND NOT(instr(1))))) ;
end behave;

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