mico8.vhm

Lattice 超精简8位软核CPU--Mico8

  DIN_RD(1) <= (not N_290 and not N_284_2 and N_284_3) or 
	  (not N_284_3 and DIN_RD_0_D(1)) or 
	  (not N_290 and DIN_RD_0_D(1)) or 
	  (N_284_2 and DIN_RD_0_D(1));
  \GEN_REG_32.U2_ISP8_RFMEM\: pmi_distributed_dpram_work_mico8_schematic_1 port map (
      WrAddress(0) => Mico8_Instr(8),
      WrAddress(1) => Mico8_Instr(9),
      WrAddress(2) => Mico8_Instr(10),
      WrAddress(3) => Mico8_Instr(11),
      WrAddress(4) => Mico8_Instr(12),
      Data(0) => DIN_RD(0),
      Data(1) => DIN_RD(1),
      Data(2) => DIN_RD(2),
      Data(3) => DIN_RD(3),
      Data(4) => DIN_RD(4),
      Data(5) => DIN_RD(5),
      Data(6) => DIN_RD(6),
      Data(7) => DIN_RD(7),
      WrClock => MicoCLK,
      WE => WREN_RD,
      WrClockEn => VCC,
      RdAddress(0) => Mico8_Instr(8),
      RdAddress(1) => Mico8_Instr(9),
      RdAddress(2) => Mico8_Instr(10),
      RdAddress(3) => Mico8_Instr(11),
      RdAddress(4) => Mico8_Instr(12),
      RdClock => MicoCLK,
      RdClockEn => VCC,
      Reset => GND,
      Q(0) => DOUT_RD(0),
      Q(1) => DOUT_RD(1),
      Q(2) => DOUT_RD(2),
      Q(3) => DOUT_RD(3),
      Q(4) => DOUT_RD(4),
      Q(5) => DOUT_RD(5),
      Q(6) => DOUT_RD(6),
      Q(7) => DOUT_RD(7));
  \GEN_REG_32.U1_ISP8_RFMEM\: pmi_distributed_dpram_work_mico8_schematic_0 port map (
      WrAddress(0) => Mico8_Instr(8),
      WrAddress(1) => Mico8_Instr(9),
      WrAddress(2) => Mico8_Instr(10),
      WrAddress(3) => Mico8_Instr(11),
      WrAddress(4) => Mico8_Instr(12),
      Data(0) => DIN_RD(0),
      Data(1) => DIN_RD(1),
      Data(2) => DIN_RD(2),
      Data(3) => DIN_RD(3),
      Data(4) => DIN_RD(4),
      Data(5) => DIN_RD(5),
      Data(6) => DIN_RD(6),
      Data(7) => DIN_RD(7),
      WrClock => MicoCLK,
      WE => WREN_RD,
      WrClockEn => VCC,
      RdAddress(0) => Mico8_Instr(3),
      RdAddress(1) => Mico8_Instr(4),
      RdAddress(2) => Mico8_Instr(5),
      RdAddress(3) => Mico8_Instr(6),
      RdAddress(4) => Mico8_Instr(7),
      RdClock => MicoCLK,
      RdClockEn => VCC,
      Reset => GND,
      Q(0) => DOUT_RB(0),
      Q(1) => DOUT_RB(1),
      Q(2) => DOUT_RB(2),
      Q(3) => DOUT_RB(3),
      Q(4) => DOUT_RB(4),
      Q(5) => DOUT_RB(5),
      Q(6) => DOUT_RB(6),
      Q(7) => DOUT_RB(7));
  U1_ISP8_IDEC: isp8_idec port map (
      Mico8_Instr_0 => Mico8_Instr(0),
      Mico8_Instr_2 => Mico8_Instr(2),
      Mico8_Instr_12 => Mico8_Instr(12),
      Mico8_Instr_1 => Mico8_Instr(1),
      Mico8_Instr_13 => Mico8_Instr(13),
      Mico8_Instr_17 => Mico8_Instr(17),
      Mico8_Instr_16 => Mico8_Instr(16),
      Mico8_Instr_15 => Mico8_Instr(15),
      Mico8_Instr_14 => Mico8_Instr(14),
      clri_i => CLRI_I,
      clrc => CLRC,
      setc => SETC,
      setz => SETZ,
      update_c_i => UPDATE_C_I,
      update_z_0 => UPDATE_Z_0,
      iels_ie => IELS_IE,
      iels_ls => IELS_LS,
      ca0 => CA0,
      call => CALL,
      instr_l2_1 => instr_l2_1,
      iels => IELS,
      iret => IRET,
      update_z_1 => UPDATE_Z_1,
      N_36_1 => N_36_1,
      un1_br0 => UN1_BR0,
      re => RE,
      sub => SUB,
      sc => SC,
      instr_l1_3 => INSTR_L1_3,
      N_221 => N_221,
      re_1 => RE_1,
      instr_l2_3 => INSTR_L2_3,
      GND => GND);
  U1_ISP8_ALU: isp8_alu port map (
      dout_alu(0) => DOUT_ALU(0),
      dout_alu(1) => DOUT_ALU(1),
      dout_alu(2) => DOUT_ALU(2),
      dout_alu(3) => DOUT_ALU(3),
      dout_alu(4) => DOUT_ALU(4),
      dout_alu(5) => DOUT_ALU(5),
      dout_alu(6) => DOUT_ALU(6),
      dout_alu(7) => DOUT_ALU(7),
      dout_rd(0) => DOUT_RD(0),
      dout_rd(1) => DOUT_RD(1),
      dout_rd(2) => DOUT_RD(2),
      dout_rd(3) => DOUT_RD(3),
      dout_rd(4) => DOUT_RD(4),
      dout_rd(5) => DOUT_RD(5),
      dout_rd(6) => DOUT_RD(6),
      dout_rd(7) => DOUT_RD(7),
      Mico8_Instr_17 => Mico8_Instr(17),
      Mico8_Instr_16 => Mico8_Instr(16),
      Mico8_Instr_15 => Mico8_Instr(15),
      Mico8_Instr_14 => Mico8_Instr(14),
      Mico8_Instr_0 => Mico8_Instr(0),
      Mico8_Instr_7 => Mico8_Instr(7),
      Mico8_Instr_6 => Mico8_Instr(6),
      Mico8_Instr_5 => Mico8_Instr(5),
      Mico8_Instr_4 => Mico8_Instr(4),
      Mico8_Instr_3 => Mico8_Instr(3),
      Mico8_Instr_2 => Mico8_Instr(2),
      Mico8_Instr_13 => Mico8_Instr(13),
      Mico8_Instr_1 => Mico8_Instr(1),
      dout_rb(0) => DOUT_RB(0),
      dout_rb(1) => DOUT_RB(1),
      dout_rb(2) => DOUT_RB(2),
      dout_rb(3) => DOUT_RB(3),
      dout_rb(4) => DOUT_RB(4),
      dout_rb(5) => DOUT_RB(5),
      dout_rb(6) => DOUT_RB(6),
      dout_rb(7) => DOUT_RB(7),
      cout_alu_u_0_1 => COUT_ALU_U_0_1,
      N_221 => N_221,
      sub => SUB,
      N_140 => N_140,
      N_36_1 => N_36_1,
      instr_l2_3 => INSTR_L2_3,
      carry_flag => CARRY_FLAG_INT_19,
      GND => GND);
  U1_ISP8_FLOW_CNTL: isp8_flow_cntl port map (
      din_rd1(0) => DIN_RD1(0),
      din_rd1(1) => DIN_RD1(1),
      din_rd1(2) => DIN_RD1(2),
      din_rd1(3) => DIN_RD1(3),
      din_rd1(4) => DIN_RD1(4),
      din_rd1(5) => DIN_RD1(5),
      din_rd1(6) => DIN_RD1(6),
      din_rd1(7) => DIN_RD1(7),
      Mico8_Instr_12 => Mico8_Instr(12),
      Mico8_Instr_15 => Mico8_Instr(15),
      Mico8_Instr_14 => Mico8_Instr(14),
      Mico8_Instr_13 => Mico8_Instr(13),
      Mico8_Instr_11 => Mico8_Instr(11),
      Mico8_Instr_10 => Mico8_Instr(10),
      Mico8_Instr_8 => Mico8_Instr(8),
      Mico8_Instr_7 => Mico8_Instr(7),
      Mico8_Instr_6 => Mico8_Instr(6),
      Mico8_Instr_5 => Mico8_Instr(5),
      Mico8_Instr_4 => Mico8_Instr(4),
      Mico8_Instr_3 => Mico8_Instr(3),
      Mico8_Instr_2 => Mico8_Instr(2),
      Mico8_Instr_1 => Mico8_Instr(1),
      Mico8_Instr_0 => Mico8_Instr(0),
      VCC => VCC,
      N_301_i => N_301_i,
      cout_alu_u_0_1 => COUT_ALU_U_0_1,
      N_140 => N_140,
      Mico_Int_c => Mico_Int_c,
      update_c_i => UPDATE_C_I,
      setc => SETC,
      clrc => CLRC,
      call => CALL,
      N_303_i => N_303_i,
      prom_addr_1_16_i_i_a2_s_0_N_5 => prom_addr_1_16_i_i_a2_s_0_N_5,
      br_enb_0_a2_0_0 => br_enb_0_a2_0_0,
      setz => SETZ,
      sc => SC,
      update_z_1 => UPDATE_Z_1,
      update_z_0 => UPDATE_Z_0,
      un1_br0 => UN1_BR0,
      ca0 => CA0,
      iels => IELS,
      instr_l2_3 => INSTR_L2_3,
      N_53_i => N_53_i,
      N_51_i => N_51_i,
      N_307_i => N_307_i,
      N_306_i => N_306_i,
      N_305_i => N_305_i,
      N_304_i => N_304_i,
      N_302_i => N_302_i,
      instr_l1_3 => INSTR_L1_3,
      sp_we_1_i_o2_N_14_i => sp_we_1_i_o2_N_14_i,
      iret => IRET,
      GND => GND,
      addr_cyc_int_1_1 => ADDR_CYC_INT_1_1,
      carry_flag => CARRY_FLAG_INT_19,
      ext_addr_cyc_int_Q => EXT_ADDR_CYC_INT_Q,
      clri_i => CLRI_I,
      INTAck_c => INTAck_c,
      g0_7 => g0_7,
      intr_reg0 => intr_reg0,
      addr_cyc => ADDR_CYC,
      data_cyc_int => DATA_CYC_INT_INT_20,
      re => RE,
      nReset_c => nReset_c,
      zero_flag => zero_flag,
      MicoCLK => MicoCLK);
  U1_ISP8_IO_CNTL: isp8_io_cntl port map (
      MicoAddr(0) => MicoAddr(0),
      MicoAddr(1) => MicoAddr(1),
      MicoAddr(2) => MicoAddr(2),
      MicoAddr(3) => MicoAddr(3),
      MicoAddr(4) => MicoAddr(4),
      MicoAddr(5) => MicoAddr(5),
      MicoAddr(6) => MicoAddr(6),
      MicoAddr(7) => MicoAddr(7),
      MicoDOut(0) => MicoDOut(0),
      MicoDOut(1) => MicoDOut(1),
      MicoDOut(2) => MicoDOut(2),
      MicoDOut(3) => MicoDOut(3),
      MicoDOut(4) => MicoDOut(4),
      MicoDOut(5) => MicoDOut(5),
      MicoDOut(6) => MicoDOut(6),
      MicoDOut(7) => MicoDOut(7),
      dout_rd(0) => DOUT_RD(0),
      dout_rd(1) => DOUT_RD(1),
      dout_rd(2) => DOUT_RD(2),
      dout_rd(3) => DOUT_RD(3),
      dout_rd(4) => DOUT_RD(4),
      dout_rd(5) => DOUT_RD(5),
      dout_rd(6) => DOUT_RD(6),
      dout_rd(7) => DOUT_RD(7),
      dout_rb(0) => DOUT_RB(0),
      dout_rb(1) => DOUT_RB(1),
      dout_rb(2) => DOUT_RB(2),
      dout_rb(3) => DOUT_RB(3),
      dout_rb(4) => DOUT_RB(4),
      dout_rb(5) => DOUT_RB(5),
      dout_rb(6) => DOUT_RB(6),
      dout_rb(7) => DOUT_RB(7),
      Mico8_Instr_7 => Mico8_Instr(7),
      Mico8_Instr_6 => Mico8_Instr(6),
      Mico8_Instr_5 => Mico8_Instr(5),
      Mico8_Instr_4 => Mico8_Instr(4),
      Mico8_Instr_3 => Mico8_Instr(3),
      Mico8_Instr_1 => Mico8_Instr(1),
      Mico8_Instr_0 => Mico8_Instr(0),
      addr_cyc_int_1_1 => ADDR_CYC_INT_1_1,
      GND => GND,
      Mico_RD_c => Mico_RD_c,
      Mico_WR_c => Mico_WR_c,
      nReset_c => nReset_c,
      ext_mem_wr => ext_mem_wr,
      MicoCLK => MicoCLK,
      iels_ls => IELS_LS,
      addr_cyc => ADDR_CYC,
      ext_addr_cyc_int_Q => EXT_ADDR_CYC_INT_Q,
      iels_ie => IELS_IE);
  NN_1 <= '0';
  NN_2 <= '1';
  carry_flag <= CARRY_FLAG_INT_19;
  data_cyc_int <= DATA_CYC_INT_INT_20;
end beh;

-- No definition of black box work.pmi_distributed_spram_work_mico8_schematic_0.syn_black_box
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity My_pll is
port(
  X2CLK_c :  out std_logic;
  GND :  in std_logic;
  nReset_c_i :  in std_logic;
  CLK_IN_c :  in std_logic;
  MicoCLK :  out std_logic);
end My_pll;

architecture beh of My_pll is
  signal MICOCLK_I : std_logic ;
  signal CLKFB_T : std_logic ;
  signal CLKOS : std_logic ;
  signal LOCK : std_logic ;
  signal NN_1 : std_logic ;
  signal VCC : std_logic ;
  component EHXPLLD
    port(
      CLKI :  in std_logic;
      CLKFB :  in std_logic;
      RST :  in std_logic;
      RSTK :  in std_logic;
      DPAMODE :  in std_logic;
      DRPAI3 :  in std_logic;
      DRPAI2 :  in std_logic;
      DRPAI1 :  in std_logic;
      DRPAI0 :  in std_logic;
      DFPAI3 :  in std_logic;
      DFPAI2 :  in std_logic;
      DFPAI1 :  in std_logic;
      DFPAI0 :  in std_logic;
      DDAMODE :  in std_logic;
      DDAIZR :  in std_logic;
      DDAILAG :  in std_logic;
      DDAIDEL0 :  in std_logic;
      DDAIDEL1 :  in std_logic;
      DDAIDEL2 :  in std_logic;
      CLKOP :  out std_logic;
      CLKOS :  out std_logic;
      CLKOK :  out std_logic;
      LOCK :  out std_logic;
      CLKINTFB :  out std_logic  );
  end component;
begin
  MicoCLK <= MICOCLK_I;
  PLLDINST_0: EHXPLLD port map (
      CLKI => CLK_IN_c,
      CLKFB => CLKFB_T,
      RST => nReset_c_i,
      RSTK => GND,
      DPAMODE => GND,
      DRPAI3 => GND,
      DRPAI2 => GND,
      DRPAI1 => GND,
      DRPAI0 => GND,
      DFPAI3 => GND,
      DFPAI2 => GND,
      DFPAI1 => GND,
      DFPAI0 => GND,
      DDAMODE => GND,
      DDAIZR => GND,
      DDAILAG => GND,
      DDAIDEL0 => GND,
      DDAIDEL1 => GND,
      DDAIDEL2 => GND,
      CLKOP => X2CLK_c,
      CLKOS => CLKOS,
      CLKOK => MICOCLK_I,
      LOCK => LOCK,
      CLKINTFB => CLKFB_T);
  NN_1 <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity ProgPRom is
port(
  Mico8_Instr : out std_logic_vector(17 downto 0);
  VCC :  in std_logic;
  MicoCLK :  in std_logic;
  data_cyc_int :  in std_logic;
  N_