mico8.vhm

Lattice 超精简8位软核CPU--Mico8

  re_1 <= RE_1_INT_8;
  instr_l2_3 <= INSTR_L2_3_INT_9;
end beh;

-- No definition of black box work.pmi_distributed_dpram_work_mico8_schematic_0.syn_black_box
-- No definition of black box work.pmi_distributed_dpram_work_mico8_schematic_1.syn_black_box
-- No definition of black box work.EHXPLLD.syn_black_box
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity isp8_core is
port(
  MicoDOut : out std_logic_vector(7 downto 0);
  MicoAddr : out std_logic_vector(7 downto 0);
  Mico8_Data_i_2_3 :  in std_logic;
  Mico8_Data_i_2_2 :  in std_logic;
  Mico8_Data_i_2_0 :  in std_logic;
  Mico8_Data_i_1 : in std_logic_vector(7 downto 4);
  Mico8_Instr : in std_logic_vector(17 downto 0);
  ext_mem_din : in std_logic_vector(7 downto 0);
  ext_mem_wr :  out std_logic;
  Mico_WR_c :  out std_logic;
  Mico_RD_c :  out std_logic;
  zero_flag :  out std_logic;
  intr_reg0 :  out std_logic;
  g0_7 :  in std_logic;
  INTAck_c :  out std_logic;
  sp_we_1_i_o2_N_14_i :  out std_logic;
  N_302_i :  out std_logic;
  N_304_i :  out std_logic;
  N_305_i :  out std_logic;
  N_306_i :  out std_logic;
  N_307_i :  out std_logic;
  N_51_i :  out std_logic;
  N_53_i :  out std_logic;
  br_enb_0_a2_0_0 :  in std_logic;
  prom_addr_1_16_i_i_a2_s_0_N_5 :  in std_logic;
  N_303_i :  out std_logic;
  Mico_Int_c :  in std_logic;
  N_301_i :  out std_logic;
  carry_flag :  out std_logic;
  instr_l2_1 :  in std_logic;
  VCC :  in std_logic;
  N_290 :  in std_logic;
  N_298 :  in std_logic;
  N_303 :  in std_logic;
  data_cyc_int :  out std_logic;
  nReset_c :  in std_logic;
  MicoCLK :  in std_logic;
  GND :  in std_logic);
end isp8_core;

architecture beh of isp8_core is
  signal DIN_RD : std_logic_vector(7 downto 0);
  signal DIN_RD1 : std_logic_vector(7 downto 0);
  signal DIN_RD_0_D : std_logic_vector(1 to 1);
  signal DOUT_ALU : std_logic_vector(7 downto 0);
  signal DIN_RD1_QN : std_logic_vector(7 downto 0);
  signal DOUT_RD : std_logic_vector(7 downto 0);
  signal DOUT_RB : std_logic_vector(7 downto 0);
  signal N_6 : std_logic ;
  signal IELS_LS : std_logic ;
  signal N_5 : std_logic ;
  signal N_3 : std_logic ;
  signal N_10 : std_logic ;
  signal N_9 : std_logic ;
  signal N_8 : std_logic ;
  signal N_7 : std_logic ;
  signal N_284_2 : std_logic ;
  signal N_27_I : std_logic ;
  signal WREN_IL_RD : std_logic ;
  signal WREN_IL_RD_QN : std_logic ;
  signal N_26_I : std_logic ;
  signal WREN_ALU_RD : std_logic ;
  signal WREN_ALU_RD_QN : std_logic ;
  signal WREN_RD : std_logic ;
  signal RE_1 : std_logic ;
  signal N_284_3 : std_logic ;
  signal IELS_IE : std_logic ;
  signal CLRI_I : std_logic ;
  signal CLRC : std_logic ;
  signal SETC : std_logic ;
  signal SETZ : std_logic ;
  signal UPDATE_C_I : std_logic ;
  signal UPDATE_Z_0 : std_logic ;
  signal CA0 : std_logic ;
  signal CALL : std_logic ;
  signal IELS : std_logic ;
  signal IRET : std_logic ;
  signal UPDATE_Z_1 : std_logic ;
  signal N_36_1 : std_logic ;
  signal UN1_BR0 : std_logic ;
  signal RE : std_logic ;
  signal SUB : std_logic ;
  signal SC : std_logic ;
  signal INSTR_L1_3 : std_logic ;
  signal N_221 : std_logic ;
  signal INSTR_L2_3 : std_logic ;
  signal COUT_ALU_U_0_1 : std_logic ;
  signal N_140 : std_logic ;
  signal ADDR_CYC_INT_1_1 : std_logic ;
  signal CARRY_FLAG_INT_19 : std_logic ;
  signal EXT_ADDR_CYC_INT_Q : std_logic ;
  signal ADDR_CYC : std_logic ;
  signal DATA_CYC_INT_INT_20 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component pmi_distributed_dpram_work_mico8_schematic_1
    port(
      WrAddress : in std_logic_vector(4 downto 0);
      Data : in std_logic_vector(7 downto 0);
      WrClock :  in std_logic;
      WE :  in std_logic;
      WrClockEn :  in std_logic;
      RdAddress : in std_logic_vector(4 downto 0);
      RdClock :  in std_logic;
      RdClockEn :  in std_logic;
      Reset :  in std_logic;
      Q : out std_logic_vector(7 downto 0)  );
  end component;
  component pmi_distributed_dpram_work_mico8_schematic_0
    port(
      WrAddress : in std_logic_vector(4 downto 0);
      Data : in std_logic_vector(7 downto 0);
      WrClock :  in std_logic;
      WE :  in std_logic;
      WrClockEn :  in std_logic;
      RdAddress : in std_logic_vector(4 downto 0);
      RdClock :  in std_logic;
      RdClockEn :  in std_logic;
      Reset :  in std_logic;
      Q : out std_logic_vector(7 downto 0)  );
  end component;
  component isp8_idec
    port(
      Mico8_Instr_0 :  in std_logic;
      Mico8_Instr_2 :  in std_logic;
      Mico8_Instr_12 :  in std_logic;
      Mico8_Instr_1 :  in std_logic;
      Mico8_Instr_13 :  in std_logic;
      Mico8_Instr_17 :  in std_logic;
      Mico8_Instr_16 :  in std_logic;
      Mico8_Instr_15 :  in std_logic;
      Mico8_Instr_14 :  in std_logic;
      clri_i :  out std_logic;
      clrc :  out std_logic;
      setc :  out std_logic;
      setz :  out std_logic;
      update_c_i :  out std_logic;
      update_z_0 :  out std_logic;
      iels_ie :  out std_logic;
      iels_ls :  out std_logic;
      ca0 :  out std_logic;
      call :  out std_logic;
      instr_l2_1 :  in std_logic;
      iels :  out std_logic;
      iret :  out std_logic;
      update_z_1 :  out std_logic;
      N_36_1 :  out std_logic;
      un1_br0 :  out std_logic;
      re :  out std_logic;
      sub :  out std_logic;
      sc :  out std_logic;
      instr_l1_3 :  out std_logic;
      N_221 :  out std_logic;
      re_1 :  out std_logic;
      instr_l2_3 :  out std_logic;
      GND :  in std_logic  );
  end component;
  component isp8_alu
    port(
      dout_alu : out std_logic_vector(7 downto 0);
      dout_rd : in std_logic_vector(7 downto 0);
      Mico8_Instr_17 :  in std_logic;
      Mico8_Instr_16 :  in std_logic;
      Mico8_Instr_15 :  in std_logic;
      Mico8_Instr_14 :  in std_logic;
      Mico8_Instr_0 :  in std_logic;
      Mico8_Instr_7 :  in std_logic;
      Mico8_Instr_6 :  in std_logic;
      Mico8_Instr_5 :  in std_logic;
      Mico8_Instr_4 :  in std_logic;
      Mico8_Instr_3 :  in std_logic;
      Mico8_Instr_2 :  in std_logic;
      Mico8_Instr_13 :  in std_logic;
      Mico8_Instr_1 :  in std_logic;
      dout_rb : in std_logic_vector(7 downto 0);
      cout_alu_u_0_1 :  out std_logic;
      N_221 :  in std_logic;
      sub :  in std_logic;
      N_140 :  out std_logic;
      N_36_1 :  in std_logic;
      instr_l2_3 :  in std_logic;
      carry_flag :  in std_logic;
      GND :  in std_logic  );
  end component;
  component isp8_flow_cntl
    port(
      din_rd1 : in std_logic_vector(7 downto 0);
      Mico8_Instr_12 :  in std_logic;
      Mico8_Instr_15 :  in std_logic;
      Mico8_Instr_14 :  in std_logic;
      Mico8_Instr_13 :  in std_logic;
      Mico8_Instr_11 :  in std_logic;
      Mico8_Instr_10 :  in std_logic;
      Mico8_Instr_8 :  in std_logic;
      Mico8_Instr_7 :  in std_logic;
      Mico8_Instr_6 :  in std_logic;
      Mico8_Instr_5 :  in std_logic;
      Mico8_Instr_4 :  in std_logic;
      Mico8_Instr_3 :  in std_logic;
      Mico8_Instr_2 :  in std_logic;
      Mico8_Instr_1 :  in std_logic;
      Mico8_Instr_0 :  in std_logic;
      VCC :  in std_logic;
      N_301_i :  out std_logic;
      cout_alu_u_0_1 :  in std_logic;
      N_140 :  in std_logic;
      Mico_Int_c :  in std_logic;
      update_c_i :  in std_logic;
      setc :  in std_logic;
      clrc :  in std_logic;
      call :  in std_logic;
      N_303_i :  out std_logic;
      prom_addr_1_16_i_i_a2_s_0_N_5 :  in std_logic;
      br_enb_0_a2_0_0 :  in std_logic;
      setz :  in std_logic;
      sc :  in std_logic;
      update_z_1 :  in std_logic;
      update_z_0 :  in std_logic;
      un1_br0 :  in std_logic;
      ca0 :  in std_logic;
      iels :  in std_logic;
      instr_l2_3 :  in std_logic;
      N_53_i :  out std_logic;
      N_51_i :  out std_logic;
      N_307_i :  out std_logic;
      N_306_i :  out std_logic;
      N_305_i :  out std_logic;
      N_304_i :  out std_logic;
      N_302_i :  out std_logic;
      instr_l1_3 :  in std_logic;
      sp_we_1_i_o2_N_14_i :  out std_logic;
      iret :  in std_logic;
      GND :  in std_logic;
      addr_cyc_int_1_1 :  in std_logic;
      carry_flag :  out std_logic;
      ext_addr_cyc_int_Q :  out std_logic;
      clri_i :  in std_logic;
      INTAck_c :  out std_logic;
      g0_7 :  in std_logic;
      intr_reg0 :  out std_logic;
      addr_cyc :  out std_logic;
      data_cyc_int :  out std_logic;
      re :  in std_logic;
      nReset_c :  in std_logic;
      zero_flag :  out std_logic;
      MicoCLK :  in std_logic  );
  end component;
  component isp8_io_cntl
    port(
      MicoAddr : out std_logic_vector(7 downto 0);
      MicoDOut : out std_logic_vector(7 downto 0);
      dout_rd : in std_logic_vector(7 downto 0);
      dout_rb : in std_logic_vector(7 downto 0);
      Mico8_Instr_7 :  in std_logic;
      Mico8_Instr_6 :  in std_logic;
      Mico8_Instr_5 :  in std_logic;
      Mico8_Instr_4 :  in std_logic;
      Mico8_Instr_3 :  in std_logic;
      Mico8_Instr_1 :  in std_logic;
      Mico8_Instr_0 :  in std_logic;
      addr_cyc_int_1_1 :  out std_logic;
      GND :  in std_logic;
      Mico_RD_c :  out std_logic;
      Mico_WR_c :  out std_logic;
      nReset_c :  in std_logic;
      ext_mem_wr :  out std_logic;
      MicoCLK :  in std_logic;
      iels_ls :  in std_logic;
      addr_cyc :  in std_logic;
      ext_addr_cyc_int_Q :  in std_logic;
      iels_ie :  in std_logic  );
  end component;
begin
  DIN_RD(3) <= (N_6 and not IELS_LS) or 
	  (N_6 and not Mico8_Instr(0)) or 
	  (ext_mem_din(3) and Mico8_Instr(0) and IELS_LS);
  DIN_RD(2) <= (N_5 and not IELS_LS) or 
	  (N_5 and not Mico8_Instr(0)) or 
	  (ext_mem_din(2) and Mico8_Instr(0) and IELS_LS);
  DIN_RD(0) <= (N_3 and not IELS_LS) or 
	  (N_3 and not Mico8_Instr(0)) or 
	  (ext_mem_din(0) and Mico8_Instr(0) and IELS_LS);
  DIN_RD(7) <= (N_10 and not IELS_LS) or 
	  (N_10 and not Mico8_Instr(0)) or 
	  (ext_mem_din(7) and Mico8_Instr(0) and IELS_LS);
  DIN_RD(6) <= (N_9 and not IELS_LS) or 
	  (N_9 and not Mico8_Instr(0)) or 
	  (ext_mem_din(6) and Mico8_Instr(0) and IELS_LS);
  DIN_RD(5) <= (N_8 and not IELS_LS) or 
	  (N_8 and not Mico8_Instr(0)) or 
	  (ext_mem_din(5) and Mico8_Instr(0) and IELS_LS);
  DIN_RD(4) <= (N_7 and not IELS_LS) or 
	  (N_7 and not Mico8_Instr(0)) or 
	  (ext_mem_din(4) and Mico8_Instr(0) and IELS_LS);
  N_27_I <= (not N_284_2) or 
	  (Mico8_Instr(0) and IELS_LS);
  DIN_RD_0_D(1) <= (DIN_RD1(1) and not IELS_LS) or 
	  (DIN_RD1(1) and not Mico8_Instr(0)) or 
	  (ext_mem_din(1) and Mico8_Instr(0) and IELS_LS);
  WREN_IL_RD_REG: FD1S3AX port map (
      D => N_27_I,
      CK => MicoCLK,
      Q => WREN_IL_RD);
  WREN_ALU_RD_REG: FD1S3AX port map (
      D => N_26_I,
      CK => MicoCLK,
      Q => WREN_ALU_RD);
  \DIN_RD1[0]_REG\: FD1S3AX port map (
      D => DOUT_ALU(0),
      CK => MicoCLK,
      Q => DIN_RD1(0));
  \DIN_RD1[1]_REG\: FD1S3AX port map (
      D => DOUT_ALU(1),
      CK => MicoCLK,
      Q => DIN_RD1(1));
  \DIN_RD1[2]_REG\: FD1S3AX port map (
      D => DOUT_ALU(2),
      CK => MicoCLK,
      Q => DIN_RD1(2));
  \DIN_RD1[3]_REG\: FD1S3AX port map (
      D => DOUT_ALU(3),
      CK => MicoCLK,
      Q => DIN_RD1(3));
  \DIN_RD1[4]_REG\: FD1S3AX port map (
      D => DOUT_ALU(4),
      CK => MicoCLK,
      Q => DIN_RD1(4));
  \DIN_RD1[5]_REG\: FD1S3AX port map (
      D => DOUT_ALU(5),
      CK => MicoCLK,
      Q => DIN_RD1(5));
  \DIN_RD1[6]_REG\: FD1S3AX port map (
      D => DOUT_ALU(6),
      CK => MicoCLK,
      Q => DIN_RD1(6));
  \DIN_RD1[7]_REG\: FD1S3AX port map (
      D => DOUT_ALU(7),
      CK => MicoCLK,
      Q => DIN_RD1(7));
  WREN_RD <= (WREN_ALU_RD and DATA_CYC_INT_INT_20) or 
	  (WREN_IL_RD and DATA_CYC_INT_INT_20);
  N_26_I <= (not Mico8_Instr(17)) or 
	  (RE_1 and not Mico8_Instr(13) and not Mico8_Instr(16));
  N_284_3 <= (not Mico8_Instr(0)) or 
	  (not IELS_LS);
  N_284_2 <= (not Mico8_Instr(0)) or 
	  (not IELS_IE);
  N_7 <= (not Mico8_Data_i_1(4) and not N_303 and not N_284_2) or 
	  (DIN_RD1(4) and N_284_2);
  N_8 <= (not Mico8_Data_i_1(5) and not N_303 and not N_284_2) or 
	  (DIN_RD1(5) and N_284_2);
  N_10 <= (not Mico8_Data_i_1(7) and not N_303 and not N_284_2) or 
	  (DIN_RD1(7) and N_284_2);
  N_9 <= (not Mico8_Data_i_1(6) and not N_303 and not N_284_2) or 
	  (DIN_RD1(6) and N_284_2);
  N_3 <= (not Mico8_Data_i_2_0 and not N_298 and not N_284_2) or 
	  (DIN_RD1(0) and N_284_2);
  N_5 <= (not Mico8_Data_i_2_2 and not N_298 and not N_284_2) or 
	  (DIN_RD1(2) and N_284_2);
  N_6 <= (not Mico8_Data_i_2_3 and not N_298 and not N_284_2) or 
	  (DIN_RD1(3) and N_284_2);