mico8.vhm

Lattice 超精简8位软核CPU--Mico8

      SP => DATA_CYC_INT_INT_17,
      CK => MicoCLK,
      Q => PC(1));
  \PC[2]_REG\: FD1P3AX port map (
      D => N_59_I,
      SP => DATA_CYC_INT_INT_17,
      CK => MicoCLK,
      Q => PC(2));
  \PC[3]_REG\: FD1P3AX port map (
      D => N_61_I,
      SP => DATA_CYC_INT_INT_17,
      CK => MicoCLK,
      Q => PC(3));
  \PC[4]_REG\: FD1P3AX port map (
      D => N_63_I,
      SP => DATA_CYC_INT_INT_17,
      CK => MicoCLK,
      Q => PC(4));
  \PC[5]_REG\: FD1P3AX port map (
      D => N_65_I,
      SP => DATA_CYC_INT_INT_17,
      CK => MicoCLK,
      Q => PC(5));
  \PC[6]_REG\: FD1P3AX port map (
      D => N_68_I,
      SP => DATA_CYC_INT_INT_17,
      CK => MicoCLK,
      Q => PC(6));
  \PC[7]_REG\: FD1P3AX port map (
      D => N_70_I,
      SP => DATA_CYC_INT_INT_17,
      CK => MicoCLK,
      Q => PC(7));
  \PC[8]_REG\: FD1P3AX port map (
      D => N_73_I,
      SP => DATA_CYC_INT_INT_17,
      CK => MicoCLK,
      Q => PC(8));
  INTR_REG0_REG: FD1P3AX port map (
      D => INTR_REG0_1,
      SP => ADDR_CYC_INT_16,
      CK => MicoCLK,
      Q => INTR_REG0_INT_15);
  INTR_ACK_INT_REG: FD1P3AX port map (
      D => g0_7,
      SP => N_20,
      CK => MicoCLK,
      Q => INTACK_C_INT_14);
  IE_FLAG_REG: FD1P3AX port map (
      D => clri_i,
      SP => N_287_I,
      CK => MicoCLK,
      Q => IE_FLAG);
  EXT_ADDR_CYC_INT_REG: FD1S3AX port map (
      D => UN3_EXT_ADDR_CYC_INT_0_A2,
      CK => MicoCLK,
      Q => EXT_ADDR_CYC_INT_Q_INT_13);
  DATA_CYC_INT_REG: FD1S3AX port map (
      D => N_18,
      CK => MicoCLK,
      Q => DATA_CYC_INT_INT_17);
  CARRY_FLAG_INT_REG: FD1P3AX port map (
      D => CARRY_FLAG_INT_1_1,
      SP => N_286_I,
      CK => MicoCLK,
      Q => CARRY_FLAG_INT_12);
  BR_ENB_REG_REG: FD1P3AX port map (
      D => N_280_I,
      SP => ADDR_CYC_INT_16,
      CK => MicoCLK,
      Q => BR_ENB_REG);
  \ADDR_JMP_REG[0]_REG\: FD1P3AX port map (
      D => Mico8_Instr_0,
      SP => ADDR_CYC_INT_16,
      CK => MicoCLK,
      Q => ADDR_JMP_REG(0));
  \ADDR_JMP_REG[1]_REG\: FD1P3AX port map (
      D => Mico8_Instr_1,
      SP => ADDR_CYC_INT_16,
      CK => MicoCLK,
      Q => ADDR_JMP_REG(1));
  \ADDR_JMP_REG[2]_REG\: FD1P3AX port map (
      D => Mico8_Instr_2,
      SP => ADDR_CYC_INT_16,
      CK => MicoCLK,
      Q => ADDR_JMP_REG(2));
  \ADDR_JMP_REG[3]_REG\: FD1P3AX port map (
      D => Mico8_Instr_3,
      SP => ADDR_CYC_INT_16,
      CK => MicoCLK,
      Q => ADDR_JMP_REG(3));
  \ADDR_JMP_REG[4]_REG\: FD1P3AX port map (
      D => Mico8_Instr_4,
      SP => ADDR_CYC_INT_16,
      CK => MicoCLK,
      Q => ADDR_JMP_REG(4));
  \ADDR_JMP_REG[5]_REG\: FD1P3AX port map (
      D => Mico8_Instr_5,
      SP => ADDR_CYC_INT_16,
      CK => MicoCLK,
      Q => ADDR_JMP_REG(5));
  \ADDR_JMP_REG[6]_REG\: FD1P3AX port map (
      D => Mico8_Instr_6,
      SP => ADDR_CYC_INT_16,
      CK => MicoCLK,
      Q => ADDR_JMP_REG(6));
  \ADDR_JMP_REG[7]_REG\: FD1P3AX port map (
      D => Mico8_Instr_7,
      SP => ADDR_CYC_INT_16,
      CK => MicoCLK,
      Q => ADDR_JMP_REG(7));
  \ADDR_JMP_REG[8]_REG\: FD1P3AX port map (
      D => Mico8_Instr_8,
      SP => ADDR_CYC_INT_16,
      CK => MicoCLK,
      Q => ADDR_JMP_REG(8));
  ADDR_CYC_INT_REG: FD1S3AX port map (
      D => addr_cyc_int_1_1,
      CK => MicoCLK,
      Q => ADDR_CYC_INT_16);
  UN1_STACK_PTR_P4 <= (N_24_I and UN1_ADDR_CYC_INT_I_A2_1(2) and STACK_PTR(0)) or 
	  (N_24_I and STACK_PTR(1)) or 
	  (UN1_ADDR_CYC_INT_I_A2_1(2) and STACK_PTR(0) and STACK_PTR(1));
  N_157 <= BR_ENB_REG and DATA_CYC_INT_INT_17;
  ZERO_FLAG_1_I_A2_0_0 <= not din_rd1(5) and not din_rd1(6);
  INTR_REG0_1_0_A2_4_TZ_0_0 <= (not Mico8_Instr_11) or 
	  (not Mico8_Instr_10);
  N_110 <= (PC_INT(1) and not RET_REG) or 
	  (DOUT_STACK(1) and RET_REG);
  N_111 <= (PC_INT(2) and not RET_REG) or 
	  (DOUT_STACK(2) and RET_REG);
  N_112 <= (PC_INT(3) and not RET_REG) or 
	  (DOUT_STACK(3) and RET_REG);
  N_113 <= (PC_INT(4) and not RET_REG) or 
	  (DOUT_STACK(4) and RET_REG);
  N_114 <= (PC_INT(5) and not RET_REG) or 
	  (DOUT_STACK(5) and RET_REG);
  N_115 <= (PC_INT(6) and not RET_REG) or 
	  (DOUT_STACK(6) and RET_REG);
  N_116 <= (PC_INT(7) and not RET_REG) or 
	  (DOUT_STACK(7) and RET_REG);
  N_117 <= (PC_INT(8) and not RET_REG) or 
	  (DOUT_STACK(8) and RET_REG);
  N_20 <= (iret and DATA_CYC_INT_INT_17) or 
	  (g0_7 and DATA_CYC_INT_INT_17);
  PROM_ADDR_I_0_M5_0_A2_0 <= INTR_REG0_INT_15 and not INTACK_C_INT_14 and DATA_CYC_INT_INT_17;
  ZERO_FLAG_1_I_A2_0_5 <= not din_rd1(0) and not din_rd1(1) and not din_rd1(2) and not din_rd1(7);
  SP_WE_1_I_O2_N_14_I_INT_11 <= (ZERO_FLAG_INT_18 and not Mico8_Instr_10 and not Mico8_Instr_11) or 
	  (not ZERO_FLAG_INT_18 and Mico8_Instr_10 and not Mico8_Instr_11) or 
	  (CARRY_FLAG_INT_12 and not Mico8_Instr_10 and Mico8_Instr_11) or 
	  (not CARRY_FLAG_INT_12 and Mico8_Instr_10 and Mico8_Instr_11);
  PC_INT(0) <= (not PC(0) and not DATA_CYC_INT_INT_17) or 
	  (not BR_ENB_REG and not PC(0)) or 
	  (ADDR_JMP_REG(0) and not PC(0)) or 
	  (not ADDR_JMP_REG(0) and BR_ENB_REG and PC(0) and DATA_CYC_INT_INT_17);
  SP_WE_1_I_O2_M8_I_1 <= (not Mico8_Instr_14) or 
	  (not Mico8_Instr_13) or 
	  (not instr_l1_3) or 
	  (Mico8_Instr_15);
  ZERO_FLAG_1_I_A2_0_6 <= not din_rd1(3) and not din_rd1(4) and ZERO_FLAG_1_I_A2_0_0 and DATA_CYC_INT_INT_17;
  N_57_I <= (not g0_7 and PC_INT(1) and not RET_REG) or 
	  (not g0_7 and DOUT_STACK(1) and RET_REG);
  N_59_I <= (not g0_7 and PC_INT(2) and not RET_REG) or 
	  (not g0_7 and DOUT_STACK(2) and RET_REG);
  N_61_I <= (not g0_7 and PC_INT(3) and not RET_REG) or 
	  (not g0_7 and DOUT_STACK(3) and RET_REG);
  N_63_I <= (not g0_7 and PC_INT(4) and not RET_REG) or 
	  (not g0_7 and DOUT_STACK(4) and RET_REG);
  N_65_I <= (not g0_7 and PC_INT(5) and not RET_REG) or 
	  (not g0_7 and DOUT_STACK(5) and RET_REG);
  N_68_I <= (not g0_7 and PC_INT(6) and not RET_REG) or 
	  (not g0_7 and DOUT_STACK(6) and RET_REG);
  N_70_I <= (not g0_7 and PC_INT(7) and not RET_REG) or 
	  (not g0_7 and DOUT_STACK(7) and RET_REG);
  N_73_I <= (not g0_7 and PC_INT(8) and not RET_REG) or 
	  (not g0_7 and DOUT_STACK(8) and RET_REG);
  N_302_i <= (N_110 and not DATA_CYC_INT_INT_17) or 
	  (N_110 and not g0_7);
  N_304_i <= (N_112 and not DATA_CYC_INT_INT_17) or 
	  (N_112 and not g0_7);
  N_305_i <= (N_113 and not DATA_CYC_INT_INT_17) or 
	  (N_113 and not g0_7);
  N_306_i <= (N_114 and not DATA_CYC_INT_INT_17) or 
	  (N_114 and not g0_7);
  N_307_i <= (N_115 and not DATA_CYC_INT_INT_17) or 
	  (N_115 and not g0_7);
  N_51_i <= (N_116 and not DATA_CYC_INT_INT_17) or 
	  (N_116 and not g0_7);
  N_53_i <= (N_117 and not DATA_CYC_INT_INT_17) or 
	  (N_117 and not g0_7);
  UN3_EXT_ADDR_CYC_INT_0_A2 <= ADDR_CYC_INT_16 and instr_l1_3 and instr_l2_3 and not Mico8_Instr_13;
  N_108 <= (PC_INT(0) and not RET_REG) or 
	  (DOUT_STACK(0) and RET_REG);
  N_18 <= (ADDR_CYC_INT_16 and not iels) or 
	  (EXT_ADDR_CYC_INT_Q_INT_13);
  INTR_REG0_1_1_TZ <= (not ca0 and not un1_br0) or 
	  (not ca0 and Mico8_Instr_12);
  N_145 <= (ZERO_FLAG_1_I_A2_0_5 and ZERO_FLAG_1_I_A2_0_6 and not update_z_0) or 
	  (ZERO_FLAG_1_I_A2_0_5 and ZERO_FLAG_1_I_A2_0_6 and update_z_1);
  N_129 <= (ADDR_CYC_INT_16 and SP_WE_1_I_O2_N_14_I_INT_11 and not SP_WE_1_I_O2_M8_I_1) or 
	  (ADDR_CYC_INT_16 and not SP_WE_1_I_O2_M8_I_1 and Mico8_Instr_12);
  N_285_I <= (not update_z_0) or 
	  (iret) or 
	  (update_z_1);
  N_287_I <= sc and not Mico8_Instr_1 and Mico8_Instr_2;
  INTR_REG0_1_4 <= (not ca0 and not un1_br0) or 
	  (INTR_REG0_1_0_A2_4_TZ_0_0) or 
	  (not ca0 and Mico8_Instr_12);
  N_77 <= (setz) or 
	  (N_145) or 
	  (iret and PUSHED_ZERO);
  N_55_I <= (not g0_7 and PC_INT(0) and not RET_REG) or 
	  (not g0_7 and DOUT_STACK(0) and RET_REG);
  N_303_i <= (N_111 and not PROM_ADDR_I_0_M5_0_A2_0) or 
	  (N_111 and not br_enb_0_a2_0_0) or 
	  (N_111 and prom_addr_1_16_i_i_a2_s_0_N_5);
  N_22 <= (N_129) or 
	  (g0_7 and DATA_CYC_INT_INT_17);
  N_24 <= (not re) or 
	  (not ADDR_CYC_INT_16) or 
	  (PROM_ADDR_I_0_M5_0_A2_0) or 
	  (UN1_ADDR_CYC_INT_I_A2_D(2));
  UN1_ADDR_CYC_INT_I_A2_1(2) <= (PROM_ADDR_I_0_M5_0_A2_0) or 
	  (UN1_ADDR_CYC_INT_I_A2_D(2)) or 
	  (ADDR_CYC_INT_16 and re);
  N_280_I <= (not br_enb_0_a2_0_0) or 
	  (call) or 
	  (un1_br0 and Mico8_Instr_12);
  N_286_I <= (not update_c_i) or 
	  (clrc) or 
	  (iret) or 
	  (setc);
  INTR_REG0_1_0_A2_2 <= not call and IE_FLAG and INTR_REG0_1_4 and Mico_Int_c;
  UN1_STACK_PTR_AXB0 <= (UN1_ADDR_CYC_INT_I_A2_1(2) and not STACK_PTR(0)) or 
	  (not UN1_ADDR_CYC_INT_I_A2_1(2) and STACK_PTR(0));
  N_24_I <= ADDR_CYC_INT_16 and not PROM_ADDR_I_0_M5_0_A2_0 and not UN1_ADDR_CYC_INT_I_A2_D(2) and re;
  N_125 <= (not clrc and N_140 and not update_c_i) or 
	  (not clrc and cout_alu_u_0_1 and not update_c_i);
  UN1_STACK_PTR_AXBXC2 <= (not N_24 and not STACK_PTR(2) and not UN1_STACK_PTR_P4) or 
	  (N_24 and STACK_PTR(2) and not UN1_STACK_PTR_P4) or 
	  (N_24 and not STACK_PTR(2) and UN1_STACK_PTR_P4) or 
	  (not N_24 and STACK_PTR(2) and UN1_STACK_PTR_P4);
  UN1_STACK_PTR_AXBXC1 <= (not N_24 and not STACK_PTR(0) and not STACK_PTR(1)) or 
	  (not N_24 and not UN1_ADDR_CYC_INT_I_A2_1(2) and not STACK_PTR(1)) or 
	  (N_24 and UN1_ADDR_CYC_INT_I_A2_1(2) and STACK_PTR(0) and not STACK_PTR(1)) or 
	  (N_24 and not STACK_PTR(0) and STACK_PTR(1)) or 
	  (N_24 and not UN1_ADDR_CYC_INT_I_A2_1(2) and STACK_PTR(1)) or 
	  (not N_24 and UN1_ADDR_CYC_INT_I_A2_1(2) and STACK_PTR(0) and STACK_PTR(1));
  CARRY_FLAG_INT_1_1 <= (setc) or 
	  (N_125) or 
	  (iret and PUSHED_CARRY);
  N_301_i <= (N_108 and not PROM_ADDR_I_0_M5_0_A2_0) or 
	  (N_108 and not br_enb_0_a2_0_0) or 
	  (N_108 and prom_addr_1_16_i_i_a2_s_0_N_5);
  INTR_REG0_1 <= (INTR_REG0_1_0_A2_2 and INTR_REG0_1_1_TZ) or 
	  (INTR_REG0_1_0_A2_2 and Mico8_Instr_10 and Mico8_Instr_11);
  UN1_STACK_PTR_AXBXC3_1 <= (N_24 and not STACK_PTR(3)) or 
	  (not N_24 and STACK_PTR(3));
  UN1_STACK_PTR_AXBXC3 <= (not STACK_PTR(2) and not UN1_STACK_PTR_AXBXC3_1 and not UN1_STACK_PTR_P4) or 
	  (not N_24_I and not UN1_STACK_PTR_AXBXC3_1 and not UN1_STACK_PTR_P4) or 
	  (N_24_I and STACK_PTR(2) and UN1_STACK_PTR_AXBXC3_1) or 
	  (not N_24_I and not STACK_PTR(2) and not UN1_STACK_PTR_AXBXC3_1) or 
	  (N_24_I and UN1_STACK_PTR_AXBXC3_1 and UN1_STACK_PTR_P4) or 
	  (STACK_PTR(2) and UN1_STACK_PTR_AXBXC3_1 and UN1_STACK_PTR_P4);
  UN1_ADDR_CYC_INT_I_A2_D_0_1(2) <= Mico8_Instr_13 and Mico8_Instr_14 and not Mico8_Instr_15 and DATA_CYC_INT_INT_17;
  UN1_ADDR_CYC_INT_I_A2_D(2) <= (SP_WE_1_I_O2_N_14_I_INT_11 and UN1_ADDR_CYC_INT_I_A2_D_0_1(2) and instr_l1_3) or 
	  (UN1_ADDR_CYC_INT_I_A2_D_0_1(2) and instr_l1_3 and Mico8_Instr_12);
  PC_INT_CRY_7_0: CCU2B 
  generic map(
    INIT0 => "0x7808",
    INIT1 => "0x6a0a",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => N_157,
    B0 => ADDR_JMP_REG(7),
    C0 => PC(7),
    D0 => VCC,
    A1 => PC(8),
    B1 => ADDR_JMP_REG(8),
    C1 => N_157,
    D1 => VCC,
    CIN => PC_INT_CRY_6,
    COUT => PC_INT_CRY_7_0_COUT,
    S0 => PC_INT(7),
    S1 => PC_INT(8));
  PC_INT_CRY_5_0: CCU2B 
  generic map(
    INIT0 => "0x7808",
    INIT1 => "0x7808",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => N_157,
    B0 => ADDR_JMP_REG(5),
    C0 => PC(5),
    D0 => VCC,
    A1 => N_157,
    B1 => ADDR_JMP_REG(6),
    C1 => PC(6),
    D1 => VCC,
    CIN => PC_INT_CRY_4,
    COUT => PC_INT_CRY_6,
    S0 => PC_INT(5),
    S1 => PC_INT(6));
  PC_INT_CRY_3_0: CCU2B 
  generic map(
    INIT0 => "0x7808",
    INIT1 => "0x7808",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => N_157,
    B0 => ADDR_JMP_REG(3),
    C0 => PC(3),
    D0 => VCC,
    A1 => N_157,
    B1 => ADDR_JMP_REG(4),
    C1 => PC(4),
    D1 => VCC,
    CIN => PC_INT_CRY_2,
    COUT => PC_INT_CRY_4,
    S0 => PC_INT(3),
    S1 => PC_INT(4));
  PC_INT_CRY_1_0: CCU2B 
  generic map(
    INIT0 => "0x7808",
    INIT1 => "0x7808",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => N_157,
    B0 => ADDR_JMP_REG(1),
    C0 => PC(1),
    D0 => VCC,
    A1 => N_157,
    B1 => ADDR_JMP_REG(2),
    C1 => PC(2),
    D1 => VCC,
    CIN => PC_INT_CRY_0,
    COUT => PC_INT_CRY_2,
    S0 => PC_INT(1),
    S1 => PC_INT(2));
  PC_INT_CRY_0_0: CCU2B 
  generic map(
    INIT0 => "0x0a0c",
    INIT1 => "0x650a",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => GND,
    B0 => GND,
    C0 => GND,
    D0 => VCC,
    A1 => PC(0),
    B1 => ADDR_JMP_REG(0),
    C1 => N_157,
    D1 => VCC,
    CIN => GND,
    COUT => PC_INT_CRY_0,
    S0 => PC_INT_CRY_0_0_S0,
    S1 => PC_INT_CRY_0_0_S1);
  U1_ISP8_STKMEM: pmi_distributed_spram_work_mico8_schematic_1 port map (
      Address(0) => STACK_PTR(0),
      Address(1) => STACK_PTR(1),
      Address(2) => STACK_PTR(2),
      Address(3) => STACK_PTR(3),
      Data(0) => PC_INT(0),
      Data(1) => PC_INT(1),
      Data(2) => PC_INT(2),
      Data(3) => PC_INT(3),
      Data(4) => PC_INT(4),
      Data(5) => PC_INT(5),
      Data(6) => PC_INT(6),