dip8_m8.vhd

Lattice 超精简8位软核CPU--Mico8

-----------------------------------------------------------------------
-- DIP8_M8.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--           
--                     Lattice Semiconductor Corporation
--                     5555 NE Moore Court
--                     Hillsboro, OR 97214
--                     U.S.A
--
--                     TEL: 1-800-Lattice (USA and Canada)
--                          408-826-6000 (other locations)
--
--                     web: http://www.latticesemi.com/
--                     email: [e-mail]
--
-- --------------------------------------------------------------------
--
-- This is a DIPSWitch input peripheral with interrupt on change function
--
-- When the input of the DIP switch changes compared to the previous clock
-- cycle, this peripheral generates an interrupt and puts the new
-- data on its output bus.
--
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
--   Ver  :| Author            :| Mod. Date :| Changes Made:
--   V1.0 :| G.M.              :| 14/01/08  :| Release
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity DIP8_M8 is
port (
	Clk : 		in std_logic;
	Reset : 	in std_logic;
	DIP8:		in std_logic_vector(7 downto 0);
	Data_Ready: 	out std_logic;
	Data_Out:	out std_logic_vector(7 downto 0)
	);
end DIP8_M8;

architecture behave of DIP8_M8 is

type 		state is (startup, active);
signal		DIP8_contr:	state;
signal prev_state:	std_logic_vector(7 downto 0);
signal prev2_state:	std_logic_vector(7 downto 0);
signal count:		integer range 0 to 3;

attribute pgroup : string;
attribute pgroup of behave : architecture is "DIP8";


begin

DIP_Check: process (Clk, Reset, DIP8)
begin
	if Reset = '1' then
		Data_Out <= (others => '0');
		Data_Ready <= '0';
		prev_state <= (others => '0');
		prev2_state <= (others => '0');
		DIP8_Contr <= Startup;
		Count <= 0;
	elsif clk'event and clk = '1' then
		case DIP8_Contr is
			when startup =>
				prev_state <= DIP8;
				prev2_state <= prev_state;
				count <= count + 1;
				if count = 3 then
					DIP8_Contr <= Active;
				end if;
				Data_Ready <= '0';
			when Active =>	
				prev_state <= DIP8;
				prev2_state <= prev_state;
				if prev_state /= prev2_state then
					Data_Out <= prev_state;
					Data_Ready <= '1';
				else 
					Data_Ready <= '0';
				end if;	
			when others =>
				DIP8_Contr <= Startup;
		end case;
	end if;
end process;

end behave;