progprom_tmpl.vhd

来自「Lattice 超精简8位软核CPU--Mico8」· VHDL 代码 · 共 16 行

-- VHDL module instantiation generated by SCUBA ispLever_v70_SP2_Build (24)
-- Module  Version: 4.1
-- Mon Mar 10 16:04:11 2008

-- parameterized module component declaration
component ProgPRom
    port (Address: in  std_logic_vector(8 downto 0); 
        OutClock: in  std_logic; OutClockEn: in  std_logic; 
        Reset: in  std_logic; Q: out  std_logic_vector(17 downto 0));
end component;

-- parameterized module component instance
__ : ProgPRom
    port map (Address(8 downto 0)=>__, OutClock=>__, OutClockEn=>__, 
        Reset=>__, Q(17 downto 0)=>__);