isp8_cfg5.vhd

Lattice 超精简8位软核CPU--Mico8

-- =============================================================================
--                           COPYRIGHT NOTICE
-- Copyright 2000-2006 (c) Lattice Semiconductor Corporation
-- ALL RIGHTS RESERVED
-- This confidential and proprietary software may be used only as authorised
-- by a licensing agreement from Lattice Semiconductor Corporation.
-- The entire notice above must be reproduced on all authorized copies and
-- copies may only be made to the extent permitted by a licensing agreement
-- from Lattice Semiconductor Corporation.
--
-- Lattice Semiconductor Corporation    TEL : 1-800-Lattice (USA and Canada)
-- 5555 NE Moore Court                        408-826-6000 (other locations)
-- Hillsboro, OR 97124                  web  : http:--www.latticesemi.com/
-- U.S.A                                email: [e-mail]
-- =============================================================================
--                         FILE DETAILS
-- Project          : isp8
-- File             : /config1/isp8_cfg.vhd
-- Title            :
-- Dependencies     : 
-- Description      : This module contains synthesis configuration information
--                  : for the VHDL version of the Mico8.    
-- =============================================================================
--                        REVISION HISTORY
-- $Revision: 1.4 $
--
-- =============================================================================

Library IEEE;
Use IEEE.Std_Logic_1164.All;

Entity isp8_cfg5 is
   Port (
      -- Clock and Reset Inputs
      clk           : In  Std_Logic;
      rst_n         : In  Std_Logic;
      -- User Inputs
      ext_mem_ready : in  Std_Logic;
      ext_io_din    : In  Std_Logic_Vector(7 DownTo 0);
      intr          : In  Std_Logic;
      -- User Outputs
      ext_addr      : Out Std_Logic_Vector(7 DownTo 0);
      ext_addr_cyc  : out Std_Logic;
      ext_io_dout   : Out Std_Logic_Vector(7 DownTo 0);
      ext_io_wr     : Out Std_Logic;
      ext_io_rd     : Out Std_Logic;
      intr_ack      : Out Std_Logic;
-- PROM external
      prom_addr	: out std_logic_vector(8 downto 0);
--	 clk
      data_cyc	: inout std_logic;
      instr		: in std_logic_vector(17 downto 0);
      Zero		: out std_logic
      );
End isp8_cfg5;

Architecture config5 Of isp8_cfg5 Is
--
component pmi_distributed_spram is
     generic (
       pmi_addr_depth       :     integer;
       pmi_addr_width       :     integer;
       pmi_data_width       :     integer;
       pmi_regmode          :     string;
       pmi_init_file        :     string;
       pmi_init_file_format :     string;
       pmi_family           :     string;
       module_type          :     string);
    port (
     Address                : in  std_logic_vector((pmi_addr_width-1) downto 0);
     Data                   : in  std_logic_vector((pmi_data_width-1) downto 0);
     Clock                  : in  std_logic;
     ClockEn                : in  std_logic;
     WE                     : in  std_logic;
     Reset                  : in  std_logic;
     Q                      : out std_logic_vector((pmi_data_width-1) downto 0)
   );

  end component pmi_distributed_spram;

   Component isp8_core
      Generic(FAMILY_NAME  :     string;
--              PROM_FILE    :     string;
              PORT_AW      :     natural;
              EXT_AW       :     natural;
              PROM_AW      :     natural;
              PROM_AD      :     natural;
              REGISTERS_16 :     boolean;
              PGM_STACK_AW :     natural;
              PGM_STACK_AD :     natural );
      Port (
         -- Clock and Reset Inputs
         clk               : In  Std_Logic;
         rst_n             : In  Std_Logic;
         ext_mem_din       : In  Std_Logic_Vector(7 DownTo 0);
         ext_mem_ready     : in  Std_Logic;
         ext_io_din        : In  Std_Logic_Vector(7 DownTo 0);
         intr              : In  Std_Logic;
         ext_addr          : Out Std_Logic_Vector(EXT_AW-1 DownTo 0);
         ext_addr_cyc      : out Std_Logic;
         ext_dout          : Out Std_Logic_Vector(7 DownTo 0);
         ext_mem_wr        : Out Std_Logic;
         ext_mem_rd        : Out Std_Logic;
         ext_io_wr         : Out Std_Logic;
         ext_io_rd         : Out Std_Logic;
         intr_ack          : Out Std_Logic;
-- PROM external
	 prom_addr	: out std_logic_vector(8 downto 0);
--	 clk
	 data_cyc	: inout std_logic;
	 instr		: in std_logic_vector(17 downto 0);
	 Zero		: out std_logic
         );
   End Component;

signal ext_addr_int : std_logic_vector(7 DownTo 0);
signal ext_dout     : std_logic_vector(7 downto 0);
signal ext_mem_dout : std_logic_vector(7 downto 0);
signal ext_mem_din  : std_logic_vector(7 downto 0);
signal ext_mem_wr   : std_logic;
signal ext_mem_rd   : std_logic;

attribute syn_black_box : boolean;
attribute syn_black_box of pmi_distributed_spram: component is true;

Begin

   ext_addr     <= ext_addr_int;
   ext_io_dout  <= ext_dout;
   ext_mem_dout <= ext_dout;

   u1_isp8: isp8_core
      Generic Map (FAMILY_NAME        => "ECP2", 
--                   PROM_FILE          => "prom_init.hex",
                   PORT_AW            => 8,
                   EXT_AW             => 8,    
                   PROM_AW            => 9,    
                   PROM_AD            => 512,  
                   REGISTERS_16       => FALSE,
                   PGM_STACK_AW       => 4,
                   PGM_STACK_AD       => 16)
      Port Map(
         -- Clock and Reset Inputs
         clk           => clk,
         rst_n         => rst_n,
         -- User Inputs
         ext_mem_din   => ext_mem_din,
         ext_io_din    => ext_io_din,
         ext_mem_ready => ext_mem_ready,
         intr          => intr,
         -- User Outputs
         ext_addr      => ext_addr_int,
         ext_addr_cyc  => ext_addr_cyc,
         ext_dout      => ext_dout,
         ext_mem_wr    => ext_mem_wr,
         ext_mem_rd    => ext_mem_rd,
         ext_io_wr     => ext_io_wr,
         ext_io_rd     => ext_io_rd,
         intr_ack      => intr_ack,
-- PROM external
	 prom_addr	=> prom_addr,
--	 clk
	 data_cyc	=> data_cyc,
	 instr		=> instr,
	 Zero		=> Zero
         );

   U2_scratchpad : pmi_distributed_spram
      generic map (
         pmi_family           => "ECP2",
         pmi_addr_depth       => 32,
         pmi_addr_width       => 5,
         pmi_data_width       => 8,
         pmi_regmode          => "noreg",
         pmi_init_file        => "none",
         pmi_init_file_format => "binary",
         module_type          => "pmi_distributed_spram")
      port map (
         Address              => ext_addr_int(4 downto 0),
         Data                 => ext_mem_dout,
         Clock                => clk,
         ClockEn              => '1',
         WE                   => ext_mem_wr,
         Reset                => '0',
         Q                    => ext_mem_din);

End config5;
-- =============================================================================