c560ed3b5c407525a5576f335fa31e178cb1cebb.svn-base

来自「FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的」· SVN-BASE 代码 · 共 18 行

# Generated by Xilinx Architecture Wizard
# --- UCF Template Only ---
# Cut and paste these attributes into the project's UCF file, if desired
INST DCM_SP_INST CLK_FEEDBACK = 1X;
INST DCM_SP_INST CLKDV_DIVIDE = 2.0;
INST DCM_SP_INST CLKFX_DIVIDE = 1;
INST DCM_SP_INST CLKFX_MULTIPLY = 6;
INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;
INST DCM_SP_INST CLKIN_PERIOD = 40.000;
INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
INST DCM_SP_INST FACTORY_JF = C080;
INST DCM_SP_INST PHASE_SHIFT = 0;
INST DCM_SP_INST STARTUP_WAIT = FALSE;