alu8.rpt

用verilog语言写的拔河游戏机

        | | | | | | | | | | | | | | +--- LC47 |74374:43|:19
        | | | | | | | | | | | | | | | +- LC44 |74374:43|:20
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'C':
LC33 -> - - - - - - - - * - * - - * - * | - - * - - - | <-- D7
LC38 -> * - - - - - - - - - - - - - - - | - - * - - - | <-- |74374:42|:20
LC44 -> * - - - - - - - - - - - - - - - | - - * - - - | <-- |74374:43|:20

Pin
13   -> * - - - - - - - - - - - - - - - | - * * * * - | <-- ALU_BUS
67   -> - - - - - - - - - - - - - - - - | - - - - - - | <-- clk
19   -> - - - - - - - - * * * * * * * * | * * * - - - | <-- cp_t
49   -> - - - - - - - - - - * * - - - - | * * * - - - | <-- LDDR1
7    -> - - - - - - - - * * - - - - - - | * * * - - - | <-- LDDR2
14   -> - - - - - - - - - - - - - - * * | * * * - - - | <-- LDR4
17   -> - - - - - - - - - - - - * * - - | * * * - - - | <-- LDR5
68   -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN001
12   -> * - - - - - - - - - - - - - - - | - * * * * - | <-- R4_BUS
10   -> * - - - - - - - - - - - - - - - | - * * * * - | <-- R5_BUS
9    -> - * * * * * * - - - - - - - - - | - - * * - - | <-- scan_clk
8    -> * - - - - - - - - - - - - - - - | - * * * * - | <-- SW_BUS
LC1  -> - - * * * * - - - - - - - - - - | * * * * - - | <-- |cdu16:54|74163:8|p74163:sub|QA
LC52 -> - - * * * * - - - - - - - - - - | - - * * * - | <-- |cdu16:54|74163:8|p74163:sub|QB
LC60 -> - - * * * * - - - - - - - - - - | - - * * - - | <-- |cdu16:54|74163:8|p74163:sub|QC
LC54 -> - - * * * * - - - - - - - - - - | - - * * - - | <-- |cdu16:54|74163:8|p74163:sub|QD
LC58 -> - - * * * * - - - - - - - - - - | - - * * - - | <-- |cdu16:56|74163:8|p74163:sub|QA
LC55 -> - - * * * * - - - - - - - - - - | - - * * - - | <-- |cdu16:56|74163:8|p74163:sub|QB
LC63 -> - - * * * * - - - - - - - - - - | - - * * - - | <-- |cdu16:56|74163:8|p74163:sub|QC
LC62 -> * - * * * * - - - - - - - - - - | - - * * - - | <-- |cdu16:56|74163:8|p74163:sub|QD
LC57 -> - - - - - - - - - * - * * - * - | - - * - - - | <-- D6
LC72 -> - - - - - - - * - - - - - - - - | * - * - * * | <-- s2
LC73 -> - - - - - - - * - - - - - - - - | * - * - * * | <-- s3
LC90 -> * - - - - - - - - - - - - - - - | - - * - - - | <-- |74181:46|F3N
LC71 -> - - - - - - - * - - - - - - - - | - - * - * * | <-- |74181:47|:41
LC74 -> - - - - - - - * - - - - - - - - | - - * - * * | <-- |74181:47|:42
LC83 -> - - - - - - - * - - - - - - - - | - - * - - - | <-- |74181:47|:89
LC25 -> - - - - - - - * - - - - - - - - | - - * - * - | <-- |74273:44|Q3
LC19 -> - - - - - - - * - - - - - - - - | - - * - * - | <-- |74273:45|Q3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       e:\xyq\maxplus\sy4\alu8.rpt
alu8

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                       Logic cells placed in LAB 'D'
        +----------------------------- LC52 |cdu16:54|74163:8|p74163:sub|QB
        | +--------------------------- LC60 |cdu16:54|74163:8|p74163:sub|QC
        | | +------------------------- LC54 |cdu16:54|74163:8|p74163:sub|QD
        | | | +----------------------- LC58 |cdu16:56|74163:8|p74163:sub|QA
        | | | | +--------------------- LC55 |cdu16:56|74163:8|p74163:sub|QB
        | | | | | +------------------- LC63 |cdu16:56|74163:8|p74163:sub|QC
        | | | | | | +----------------- LC62 |cdu16:56|74163:8|p74163:sub|QD
        | | | | | | | +--------------- LC49 D2
        | | | | | | | | +------------- LC51 D3
        | | | | | | | | | +----------- LC53 D4
        | | | | | | | | | | +--------- LC56 D5
        | | | | | | | | | | | +------- LC57 D6
        | | | | | | | | | | | | +----- LC64 seg_a
        | | | | | | | | | | | | | +--- LC59 seg_d
        | | | | | | | | | | | | | | +- LC61 seg-f
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'D':
LC52 -> * * * * * * * - - - - - * * * | - - * * * - | <-- |cdu16:54|74163:8|p74163:sub|QB
LC60 -> - * * * * * * * - - - - * * * | - - * * - - | <-- |cdu16:54|74163:8|p74163:sub|QC
LC54 -> - - * * * * * - * - - - * * * | - - * * - - | <-- |cdu16:54|74163:8|p74163:sub|QD
LC58 -> - - - * * * * - - * - - * * * | - - * * - - | <-- |cdu16:56|74163:8|p74163:sub|QA
LC55 -> - - - - * * * - - - * - * * * | - - * * - - | <-- |cdu16:56|74163:8|p74163:sub|QB
LC63 -> - - - - - * * - - - - * * * * | - - * * - - | <-- |cdu16:56|74163:8|p74163:sub|QC
LC62 -> - - - - - - * - - - - - * * * | - - * * - - | <-- |cdu16:56|74163:8|p74163:sub|QD

Pin
13   -> - - - - - - - * * * * * - - - | - * * * * - | <-- ALU_BUS
5    -> * * * * * * * - - - - - - - - | * - - * - - | <-- cir
67   -> - - - - - - - - - - - - - - - | - - - - - - | <-- clk
22   -> * * * - - - - - - - - - - - - | * - - * - - | <-- encdu
68   -> - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN001
12   -> - - - - - - - * * * * * - - - | - * * * * - | <-- R4_BUS
10   -> - - - - - - - * * * * * - - - | - * * * * - | <-- R5_BUS
9    -> - - - - - - - - - - - - * * * | - - * * - - | <-- scan_clk
8    -> - - - - - - - * * * * * - - - | - * * * * - | <-- SW_BUS
LC1  -> * * * * * * * - - - - - * * * | * * * * - - | <-- |cdu16:54|74163:8|p74163:sub|QA
LC91 -> - - - - - - - - - - - * - - - | - - - * - - | <-- |74181:46|F2N
LC93 -> - - - - - - - - - - * - - - - | - - - * - - | <-- |74181:46|F1N
LC68 -> - - - - - - - - - * - - - - - | - - - * - - | <-- |74181:46|F0N
LC5  -> - - - - - - - - * - - - - - - | - - - * - - | <-- |74181:47|F3N
LC34 -> - - - - - - - * - - - - - - - | - - - * - - | <-- |74181:47|F2N
LC23 -> - - - - - - - * - - - - - - - | - - - * - - | <-- |74374:42|:15
LC22 -> - - - - - - - - * - - - - - - | - - - * - - | <-- |74374:42|:16
LC21 -> - - - - - - - - - * - - - - - | - - - * - - | <-- |74374:42|:17
LC26 -> - - - - - - - - - - * - - - - | - - - * - - | <-- |74374:42|:18
LC42 -> - - - - - - - - - - - * - - - | - - - * - - | <-- |74374:42|:19
LC12 -> - - - - - - - * - - - - - - - | - - - * - - | <-- |74374:43|:15
LC27 -> - - - - - - - - * - - - - - - | - - - * - - | <-- |74374:43|:16
LC29 -> - - - - - - - - - * - - - - - | - - - * - - | <-- |74374:43|:17
LC32 -> - - - - - - - - - - * - - - - | - - - * - - | <-- |74374:43|:18
LC47 -> - - - - - - - - - - - * - - - | - - - * - - | <-- |74374:43|:19


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       e:\xyq\maxplus\sy4\alu8.rpt
alu8

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                                     Logic cells placed in LAB 'E'
        +--------------------------- LC65 D1
        | +------------------------- LC67 ~PIN002
        | | +----------------------- LC80 s0
        | | | +--------------------- LC77 s1
        | | | | +------------------- LC72 s2
        | | | | | +----------------- LC73 s3
        | | | | | | +--------------- LC68 |74181:46|F0N
        | | | | | | | +------------- LC79 |74181:46|:88
        | | | | | | | | +----------- LC66 |74181:47|:39
        | | | | | | | | | +--------- LC70 |74181:47|:40
        | | | | | | | | | | +------- LC71 |74181:47|:41
        | | | | | | | | | | | +----- LC74 |74181:47|:42
        | | | | | | | | | | | | +--- LC76 |74181:47|:49
        | | | | | | | | | | | | | +- LC78 |74181:47|:50
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'E':
LC80 -> - - * * * * - - * - * - - * | * - - - * * | <-- s0
LC77 -> - - - * * * - - * - * - - * | * - - - * * | <-- s1
LC72 -> - - - - * * - - - * - * * - | * - * - * * | <-- s2
LC73 -> - - - - - * - - - * - * * - | * - * - * * | <-- s3
LC66 -> - - - - - - * * - - - - - - | * - - - * * | <-- |74181:47|:39
LC70 -> - - - - - - * * - - - - - - | * - - - * * | <-- |74181:47|:40
LC71 -> - - - - - - * * - - - - - - | - - * - * * | <-- |74181:47|:41
LC74 -> - - - - - - * * - - - - - - | - - * - * * | <-- |74181:47|:42
LC76 -> - - - - - - * * - - - - - - | * - - - * * | <-- |74181:47|:49
LC78 -> - - - - - - * * - - - - - - | * - - - * * | <-- |74181:47|:50

Pin
13   -> * * - - - - - - - - - - - - | - * * * * - | <-- ALU_BUS
18   -> - - * * * * - - - - - - - - | - - - - * - | <-- cir_181
67   -> - - - - - - - - - - - - - - | - - - - - - | <-- clk
4    -> - - - - - - * * - - - - - - | - - - - * * | <-- CN
20   -> - - * * * * - - - - - - - - | - - - - * - | <-- en_181
15   -> - - - - - - * * - - - - - - | - - - - * * | <-- M
68   -> - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN001
12   -> * * - - - - - - - - - - - - | - * * * * - | <-- R4_BUS
10   -> * * - - - - - - - - - - - - | - * * * * - | <-- R5_BUS
8    -> * * - - - - - - - - - - - - | - * * * * - | <-- SW_BUS
LC52 -> * - - - - - - - - - - - - - | - - * * * - | <-- |cdu16:54|74163:8|p74163:sub|QB
LC3  -> - - - - - - * * - - - - - - | - - - - * * | <-- |74181:46|:37
LC4  -> - - - - - - * * - - - - - - | - - - - * * | <-- |74181:46|:38
LC9  -> - - - - - - * * - - - - - - | - - - - * * | <-- |74181:47|:37
LC11 -> - - - - - - * * - - - - - - | - - - - * * | <-- |74181:47|:38
LC6  -> * - - - - - - - - - - - - - | - - - - * - | <-- |74181:47|F1N
LC20 -> - - - - - - - - - - - - * * | * - - - * - | <-- |74273:44|Q4
LC25 -> - - - - - - - - - - * * - - | - - * - * - | <-- |74273:44|Q3
LC8  -> - - - - - - - - * * - - - - | * - - - * - | <-- |74273:44|Q2
LC18 -> - - - - - - - - - - - - * * | * - - - * - | <-- |74273:45|Q4
LC19 -> - - - - - - - - - - * * - - | - - * - * - | <-- |74273:45|Q3
LC2  -> - - - - - - - - * * - - - - | * - - - * - | <-- |74273:45|Q2
LC14 -> * - - - - - - - - - - - - - | - - - - * - | <-- |74374:42|:14
LC10 -> * - - - - - - - - - - - - - | - - - - * - | <-- |74374:43|:14


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       e:\xyq\maxplus\sy4\alu8.rpt
alu8

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                                         Logic cells placed in LAB 'F'
        +------------------------------- LC88 CN4
        | +----------------------------- LC95 |74181:46|:39
        | | +--------------------------- LC87 |74181:46|:40
        | | | +------------------------- LC96 |74181:46|:41
        | | | | +----------------------- LC94 |74181:46|:42
        | | | | | +--------------------- LC82 |74181:46|:49
        | | | | | | +------------------- LC85 |74181:46|:50
        | | | | | | | +----------------- LC89 |74181:46|:76
        | | | | | | | | +--------------- LC90 |74181:46|F3N
        | | | | | | | | | +------------- LC91 |74181:46|F2N
        | | | | | | | | | | +----------- LC93 |74181:46|F1N
        | | | | | | | | | | | +--------- LC92 |74181:46|:89
        | | | | | | | | | | | | +------- LC86 |74181:47|:76
        | | | | | | | | | | | | | +----- LC81 |74181:47|F0N
        | | | | | | | | | | | | | | +--- LC84 |74181:47|:88
        | | | | | | | | | | | | | | | +- LC83 |74181:47|:89
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'F':
LC95 -> * - - - - - - * - - * * - - - - | - - - - - * | <-- |74181:46|:39
LC87 -> * - - - - - - * - - * * - - - - | - - - - - * | <-- |74181:46|:40
LC96 -> * - - - - - - * - * - - - - - - | - - - - - * | <-- |74181:46|:41
LC94 -> * - - - - - - * - * - - - - - - | - - - - - * | <-- |74181:46|:42
LC82 -> * - - - - - - - * - - - - - - - | - - - - - * | <-- |74181:46|:49
LC85 -> * - - - - - - - * - - - - - - - | - - - - - * | <-- |74181:46|:50
LC89 -> - - - - - - - - * - - - - - - - | - - - - - * | <-- |74181:46|:76
LC92 -> - - - - - - - - - * - - - - - - | - - - - - * | <-- |74181:46|:89

Pin
67   -> - - - - - - - - - - - - - - - - | - - - - - - | <-- clk
4    -> * - - - - - - * - - - * * * * * | - - - - * * | <-- CN
15   -> - - - - - - - * - - - * * * * * | - - - - * * | <-- M
68   -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN001
LC80 -> - * - * - - * - - - - - - - - - | * - - - * * | <-- s0
LC77 -> - * - * - - * - - - - - - - - - | * - - - * * | <-- s1
LC72 -> - - * - * * - - * * * - - - - - | * - * - * * | <-- s2
LC73 -> - - * - * * - - * * * - - - - - | * - * - * * | <-- s3
LC3  -> * - - - - - - * - - - * - - - - | - - - - * * | <-- |74181:46|:37
LC4  -> * - - - - - - * - - - * - - - - | - - - - * * | <-- |74181:46|:38
LC79 -> - - - - - - - - - - * - - - - - | - - - - - * | <-- |74181:46|:88
LC9  -> * - - - - - - * - - - * * * * * | - - - - * * | <-- |74181:47|:37
LC11 -> * - - - - - - * - - - * * * * * | - - - - * * | <-- |74181:47|:38
LC66 -> * - - - - - - * - - - * * - - * | * - - - * * | <-- |74181:47|:39
LC70 -> * - - - - - - * - - - * * - - * | * - - - * * | <-- |74181:47|:40
LC71 -> * - - - - - - * - - - * * - - - | - - * - * * | <-- |74181:47|:41
LC74 -> * - - - - - - * - - - * * - - - | - - * - * * | <-- |74181:47|:42
LC76 -> * - - - - - - * - - - * - - - - | * - - - * * | <-- |74181:47|:49
LC78 -> * - - - - - - * - - - * - - - - | * - - - * * | <-- |74181:47|:50
LC48 -> - - - - - * * - * - - - - - - - | - - - - - * | <-- |74273:44|Q8
LC36 -> - - - * * - - - - * - - - - - - | - - - - - * | <-- |74273:44|Q7
LC28 -> - * * - - - - - - - * - - - - - | - - - - - * | <-- |74273:44|Q6
LC46 -> - - - - - * * - * - - - - - - - | - - - - - * | <-- |74273:45|Q8
LC39 -> - - - * * - - - - * - - - - - - | - - - - - * | <-- |74273:45|Q7
LC30 -> - * * - - - - - - - * - - - - - | - - - - - * | <-- |74273:45|Q6


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       e:\xyq\maxplus\sy4\alu8.rpt
alu8

** EQUATIONS **

ALU_BUS  : INPUT;
cir      : INPUT;
cir_181  : INPUT;
clk      : INPUT;
CN       : INPUT;
cp_t     : INPUT;
encdu    : INPUT;