📄 alu8.rpt
字号:
39 53 D TRI t 0 0 0 4 4 0 4 D4
40 56 D TRI t 0 0 0 4 4 0 4 D5
41 57 D TRI t 0 0 0 4 4 0 4 D6
33 33 C TRI t 0 0 0 4 4 0 4 D7
30 37 C OUTPUT t 0 0 0 1 0 0 0 GW
47 67 E OUTPUT t 0 0 0 4 0 0 0 ~PIN002
45 64 D OUTPUT t 5 1 1 1 8 0 0 seg_a
29 40 C OUTPUT t 5 0 1 1 8 0 0 seg_b
28 41 C OUTPUT t 2 0 0 1 8 0 0 seg_c
42 59 D OUTPUT t 5 0 1 1 8 0 0 seg_d
27 43 C OUTPUT t 3 0 1 1 8 0 0 seg_e
44 61 D OUTPUT t 5 1 1 1 8 0 0 seg-f
25 45 C OUTPUT t 0 0 0 1 8 0 0 seg_g
32 35 C OUTPUT t 0 0 0 1 0 0 0 SW
55 80 E FF + t 0 0 0 2 1 4 8 s0 (|cdu16:50|74163:8|p74163:sub|:34)
54 77 E FF + t 0 0 0 2 2 3 8 s1 (|cdu16:50|74163:8|p74163:sub|:35)
50 72 E FF + t 0 0 0 2 3 2 14 s2 (|cdu16:50|74163:8|p74163:sub|:36)
51 73 E FF + t 0 0 0 2 4 1 14 s3 (|cdu16:50|74163:8|p74163:sub|:37)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\xyq\maxplus\sy4\alu8.rpt
alu8
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(13) 1 A DFFE + t 0 0 0 2 1 8 8 |cdu16:54|74163:8|p74163:sub|QA (|cdu16:54|74163:8|p74163:sub|:34)
- 52 D DFFE + t 0 0 0 2 2 8 7 |cdu16:54|74163:8|p74163:sub|QB (|cdu16:54|74163:8|p74163:sub|:35)
- 60 D TFFE + t 0 0 0 2 3 8 6 |cdu16:54|74163:8|p74163:sub|QC (|cdu16:54|74163:8|p74163:sub|:36)
- 54 D TFFE + t 0 0 0 2 4 8 5 |cdu16:54|74163:8|p74163:sub|QD (|cdu16:54|74163:8|p74163:sub|:37)
- 58 D TFFE + t 0 0 0 1 5 8 4 |cdu16:56|74163:8|p74163:sub|QA (|cdu16:56|74163:8|p74163:sub|:34)
- 55 D TFFE + t 0 0 0 1 6 8 3 |cdu16:56|74163:8|p74163:sub|QB (|cdu16:56|74163:8|p74163:sub|:35)
- 63 D TFFE + t 0 0 0 1 7 8 2 |cdu16:56|74163:8|p74163:sub|QC (|cdu16:56|74163:8|p74163:sub|:36)
- 62 D TFFE + t 0 0 0 1 8 8 1 |cdu16:56|74163:8|p74163:sub|QD (|cdu16:56|74163:8|p74163:sub|:37)
- 3 A SOFT t 0 0 0 0 4 1 4 |74181:46|:37
(12) 4 A SOFT t 0 0 0 0 4 1 4 |74181:46|:38
- 95 F SOFT t 0 0 0 0 4 1 3 |74181:46|:39
- 87 F SOFT t 0 0 0 0 4 1 3 |74181:46|:40
(65) 96 F SOFT t 0 0 0 0 4 1 2 |74181:46|:41
(64) 94 F SOFT t 0 0 0 0 4 1 2 |74181:46|:42
- 82 F SOFT t 0 0 0 0 4 1 1 |74181:46|:49
- 85 F SOFT t 0 0 0 0 4 1 1 |74181:46|:50
(61) 89 F SOFT t 5 0 1 2 14 0 1 |74181:46|:76
- 90 F SOFT t 0 0 0 0 7 1 0 |74181:46|F3N (|74181:46|:84)
- 91 F SOFT t 0 0 0 0 7 1 0 |74181:46|F2N (|74181:46|:85)
- 93 F SOFT t 0 0 0 0 7 1 0 |74181:46|F1N (|74181:46|:86)
- 68 E SOFT t 7 0 0 2 10 1 0 |74181:46|F0N (|74181:46|:87)
- 79 E SOFT t 3 0 1 2 10 0 1 |74181:46|:88
(62) 92 F SOFT t 4 0 1 2 12 0 1 |74181:46|:89
(8) 9 A SOFT t 0 0 0 0 4 1 8 |74181:47|:37
- 11 A SOFT t 0 0 0 0 4 1 8 |74181:47|:38
- 66 E SOFT t 0 0 0 0 4 1 7 |74181:47|:39
- 70 E SOFT t 0 0 0 0 4 1 7 |74181:47|:40
- 71 E SOFT t 0 0 0 0 4 1 6 |74181:47|:41
- 74 E SOFT t 0 0 0 0 4 1 6 |74181:47|:42
- 76 E SOFT t 0 0 0 0 4 1 5 |74181:47|:49
- 78 E SOFT t 0 0 0 0 4 1 5 |74181:47|:50
(59) 86 F SOFT t 0 0 0 2 6 0 1 |74181:47|:76
- 5 A SOFT t 0 0 0 0 7 1 0 |74181:47|F3N (|74181:47|:84)
- 34 C SOFT t 0 0 0 0 7 1 0 |74181:47|F2N (|74181:47|:85)
(10) 6 A SOFT t 0 0 0 0 7 1 0 |74181:47|F1N (|74181:47|:86)
(56) 81 F SOFT t 0 0 0 2 2 1 0 |74181:47|F0N (|74181:47|:87)
(57) 84 F SOFT t 0 0 0 2 2 0 1 |74181:47|:88
- 83 F SOFT t 0 0 0 2 4 0 1 |74181:47|:89
(24) 48 C DFFE t 0 0 0 2 1 0 3 |74273:44|Q8 (|74273:44|:12)
- 36 C DFFE t 0 0 0 2 1 0 3 |74273:44|Q7 (|74273:44|:13)
- 28 B DFFE t 0 0 0 2 1 0 3 |74273:44|Q6 (|74273:44|:14)
(19) 24 B DFFE t 0 0 0 2 1 0 2 |74273:44|Q5 (|74273:44|:15)
- 20 B DFFE t 0 0 0 2 1 0 3 |74273:44|Q4 (|74273:44|:16)
(18) 25 B DFFE t 0 0 0 2 1 0 3 |74273:44|Q3 (|74273:44|:17)
(9) 8 A DFFE t 0 0 0 2 1 0 3 |74273:44|Q2 (|74273:44|:18)
(4) 16 A DFFE t 0 0 0 2 1 0 2 |74273:44|Q1 (|74273:44|:19)
- 46 C DFFE t 0 0 0 2 1 0 3 |74273:45|Q8 (|74273:45|:12)
- 39 C DFFE t 0 0 0 2 1 0 3 |74273:45|Q7 (|74273:45|:13)
- 30 B DFFE t 0 0 0 2 1 0 3 |74273:45|Q6 (|74273:45|:14)
- 31 B DFFE t 0 0 0 2 1 0 2 |74273:45|Q5 (|74273:45|:15)
- 18 B DFFE t 0 0 0 2 1 0 3 |74273:45|Q4 (|74273:45|:16)
(22) 19 B DFFE t 0 0 0 2 1 0 3 |74273:45|Q3 (|74273:45|:17)
- 2 A DFFE t 0 0 0 2 1 0 3 |74273:45|Q2 (|74273:45|:18)
- 13 A DFFE t 0 0 0 2 1 0 2 |74273:45|Q1 (|74273:45|:19)
- 15 A DFFE t 0 0 0 2 1 1 0 |74374:42|:13
(5) 14 A DFFE t 0 0 0 2 1 1 0 |74374:42|:14
- 23 B DFFE t 0 0 0 2 1 1 0 |74374:42|:15
- 22 B DFFE t 0 0 0 2 1 1 0 |74374:42|:16
(20) 21 B DFFE t 0 0 0 2 1 1 0 |74374:42|:17
- 26 B DFFE t 0 0 0 2 1 1 0 |74374:42|:18
- 42 C DFFE t 0 0 0 2 1 1 0 |74374:42|:19
- 38 C DFFE t 0 0 0 2 1 1 0 |74374:42|:20
- 7 A DFFE t 0 0 0 2 1 1 0 |74374:43|:13
- 10 A DFFE t 0 0 0 2 1 1 0 |74374:43|:14
(7) 12 A DFFE t 0 0 0 2 1 1 0 |74374:43|:15
(17) 27 B DFFE t 0 0 0 2 1 1 0 |74374:43|:16
(15) 29 B DFFE t 0 0 0 2 1 1 0 |74374:43|:17
(14) 32 B DFFE t 0 0 0 2 1 1 0 |74374:43|:18
- 47 C DFFE t 0 0 0 2 1 1 0 |74374:43|:19
- 44 C DFFE t 0 0 0 2 1 1 0 |74374:43|:20
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\xyq\maxplus\sy4\alu8.rpt
alu8
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC1 |cdu16:54|74163:8|p74163:sub|QA
| +----------------------------- LC3 |74181:46|:37
| | +--------------------------- LC4 |74181:46|:38
| | | +------------------------- LC9 |74181:47|:37
| | | | +----------------------- LC11 |74181:47|:38
| | | | | +--------------------- LC5 |74181:47|F3N
| | | | | | +------------------- LC6 |74181:47|F1N
| | | | | | | +----------------- LC8 |74273:44|Q2
| | | | | | | | +--------------- LC16 |74273:44|Q1
| | | | | | | | | +------------- LC2 |74273:45|Q2
| | | | | | | | | | +----------- LC13 |74273:45|Q1
| | | | | | | | | | | +--------- LC15 |74374:42|:13
| | | | | | | | | | | | +------- LC14 |74374:42|:14
| | | | | | | | | | | | | +----- LC7 |74374:43|:13
| | | | | | | | | | | | | | +--- LC10 |74374:43|:14
| | | | | | | | | | | | | | | +- LC12 |74374:43|:15
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'A':
LC1 -> * - - - - - - - - - - - - - - - | * * * * - - | <-- |cdu16:54|74163:8|p74163:sub|QA
LC8 -> - - - - - - * - - - - - - - - - | * - - - * - | <-- |74273:44|Q2
LC16 -> - - - * * - - - - - - - - - - - | * - - - - - | <-- |74273:44|Q1
LC2 -> - - - - - - * - - - - - - - - - | * - - - * - | <-- |74273:45|Q2
LC13 -> - - - * * - - - - - - - - - - - | * - - - - - | <-- |74273:45|Q1
Pin
5 -> * - - - - - - - - - - - - - - - | * - - * - - | <-- cir
67 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- clk
19 -> - - - - - - - * * * * * * * * * | * * * - - - | <-- cp_t
22 -> * - - - - - - - - - - - - - - - | * - - * - - | <-- encdu
49 -> - - - - - - - - - * * - - - - - | * * * - - - | <-- LDDR1
7 -> - - - - - - - * * - - - - - - - | * * * - - - | <-- LDDR2
14 -> - - - - - - - - - - - - - * * * | * * * - - - | <-- LDR4
17 -> - - - - - - - - - - - * * - - - | * * * - - - | <-- LDR5
68 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN001
LC17 -> - - - - - - - - * - * * - * - - | * - - - - - | <-- D0
LC65 -> - - - - - - - * - * - - * - * - | * - - - - - | <-- D1
LC49 -> - - - - - - - - - - - - - - - * | * * - - - - | <-- D2
LC80 -> - * - * - - - - - - - - - - - - | * - - - * * | <-- s0
LC77 -> - * - * - - - - - - - - - - - - | * - - - * * | <-- s1
LC72 -> - - * - * * * - - - - - - - - - | * - * - * * | <-- s2
LC73 -> - - * - * * * - - - - - - - - - | * - * - * * | <-- s3
LC66 -> - - - - - - * - - - - - - - - - | * - - - * * | <-- |74181:47|:39
LC70 -> - - - - - - * - - - - - - - - - | * - - - * * | <-- |74181:47|:40
LC76 -> - - - - - * - - - - - - - - - - | * - - - * * | <-- |74181:47|:49
LC78 -> - - - - - * - - - - - - - - - - | * - - - * * | <-- |74181:47|:50
LC86 -> - - - - - * - - - - - - - - - - | * - - - - - | <-- |74181:47|:76
LC84 -> - - - - - - * - - - - - - - - - | * - - - - - | <-- |74181:47|:88
LC24 -> - * * - - - - - - - - - - - - - | * - - - - - | <-- |74273:44|Q5
LC20 -> - - - - - * - - - - - - - - - - | * - - - * - | <-- |74273:44|Q4
LC31 -> - * * - - - - - - - - - - - - - | * - - - - - | <-- |74273:45|Q5
LC18 -> - - - - - * - - - - - - - - - - | * - - - * - | <-- |74273:45|Q4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\xyq\maxplus\sy4\alu8.rpt
alu8
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC17 D0
| +----------------------------- LC28 |74273:44|Q6
| | +--------------------------- LC24 |74273:44|Q5
| | | +------------------------- LC20 |74273:44|Q4
| | | | +----------------------- LC25 |74273:44|Q3
| | | | | +--------------------- LC30 |74273:45|Q6
| | | | | | +------------------- LC31 |74273:45|Q5
| | | | | | | +----------------- LC18 |74273:45|Q4
| | | | | | | | +--------------- LC19 |74273:45|Q3
| | | | | | | | | +------------- LC23 |74374:42|:15
| | | | | | | | | | +----------- LC22 |74374:42|:16
| | | | | | | | | | | +--------- LC21 |74374:42|:17
| | | | | | | | | | | | +------- LC26 |74374:42|:18
| | | | | | | | | | | | | +----- LC27 |74374:43|:16
| | | | | | | | | | | | | | +--- LC29 |74374:43|:17
| | | | | | | | | | | | | | | +- LC32 |74374:43|:18
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'B':
Pin
13 -> * - - - - - - - - - - - - - - - | - * * * * - | <-- ALU_BUS
67 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- clk
19 -> - * * * * * * * * * * * * * * * | * * * - - - | <-- cp_t
49 -> - - - - - * * * * - - - - - - - | * * * - - - | <-- LDDR1
7 -> - * * * * - - - - - - - - - - - | * * * - - - | <-- LDDR2
14 -> - - - - - - - - - - - - - * * * | * * * - - - | <-- LDR4
17 -> - - - - - - - - - * * * * - - - | * * * - - - | <-- LDR5
68 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN001
12 -> * - - - - - - - - - - - - - - - | - * * * * - | <-- R4_BUS
10 -> * - - - - - - - - - - - - - - - | - * * * * - | <-- R5_BUS
8 -> * - - - - - - - - - - - - - - - | - * * * * - | <-- SW_BUS
LC1 -> * - - - - - - - - - - - - - - - | * * * * - - | <-- |cdu16:54|74163:8|p74163:sub|QA
LC49 -> - - - - * - - - * * - - - - - - | * * - - - - | <-- D2
LC51 -> - - - * - - - * - - * - - * - - | - * - - - - | <-- D3
LC53 -> - - * - - - * - - - - * - - * - | - * - - - - | <-- D4
LC56 -> - * - - - * - - - - - - * - - * | - * - - - - | <-- D5
LC81 -> * - - - - - - - - - - - - - - - | - * - - - - | <-- |74181:47|F0N
LC15 -> * - - - - - - - - - - - - - - - | - * - - - - | <-- |74374:42|:13
LC7 -> * - - - - - - - - - - - - - - - | - * - - - - | <-- |74374:43|:13
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\xyq\maxplus\sy4\alu8.rpt
alu8
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC33 D7
| +----------------------------- LC37 GW
| | +--------------------------- LC40 seg_b
| | | +------------------------- LC41 seg_c
| | | | +----------------------- LC43 seg_e
| | | | | +--------------------- LC45 seg_g
| | | | | | +------------------- LC35 SW
| | | | | | | +----------------- LC34 |74181:47|F2N
| | | | | | | | +--------------- LC48 |74273:44|Q8
| | | | | | | | | +------------- LC36 |74273:44|Q7
| | | | | | | | | | +----------- LC46 |74273:45|Q8
| | | | | | | | | | | +--------- LC39 |74273:45|Q7
| | | | | | | | | | | | +------- LC42 |74374:42|:19
| | | | | | | | | | | | | +----- LC38 |74374:42|:20
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