📄 alu8.rpt
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Project Information e:\xyq\maxplus\sy4\alu8.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 04/19/2008 22:10:40
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
alu8 EPM7096LC68-7 18 15 8 93 40 96 %
User Pins: 17 14 8
Project Information e:\xyq\maxplus\sy4\alu8.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information e:\xyq\maxplus\sy4\alu8.rpt
** MULTIPLE PIN CONNECTIONS **
For node name '|74244:48|~26~1~2~3' (Same as node '~PIN001')
For node name '|74244:48|~26~1~2~2' (Same as node '~PIN002')
Connect: {alu8@68, alu8@47}
Project Information e:\xyq\maxplus\sy4\alu8.rpt
** FILE HIERARCHY **
|74244:48|
|74244:49|
|74181:46|
|74181:47|
|74273:44|
|74273:45|
|74374:42|
|74374:43|
|cdu16:50|
|cdu16:50|74163:8|
|cdu16:50|74163:8|p74163:sub|
|cdu16:56|
|cdu16:56|74163:8|
|cdu16:56|74163:8|p74163:sub|
|cdu16:54|
|cdu16:54|74163:8|
|cdu16:54|74163:8|p74163:sub|
|saomiao:78|
|saomiao:78|74157:1|
|bcd_7seg:81|
Device-Specific Information: e:\xyq\maxplus\sy4\alu8.rpt
alu8
***** Logic for device 'alu8' compiled without errors.
Device: EPM7096LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: e:\xyq\maxplus\sy4\alu8.rpt
alu8
** ERROR SUMMARY **
Info: Chip 'alu8' in device 'EPM7096LC68-7' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
s R R R R
c ~ E E E E
a S V P S S S S
n W L C I E E V E E
_ _ D C N R R C R R
c B D G c I G G 0 c G V V C V V
l U R N i C N N N 0 l N E E I E E
k S 2 D r N T D D 1 k D D D O D D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
R5_BUS | 10 60 | CN4
VCCIO | 11 59 | RESERVED
R4_BUS | 12 58 | GND
ALU_BUS | 13 57 | RESERVED
LDR4 | 14 56 | RESERVED
M | 15 55 | s0
GND | 16 54 | s1
LDR5 | 17 53 | VCCIO
cir_181 | 18 EPM7096LC68-7 52 | RESERVED
cp_t | 19 51 | s3
en_181 | 20 50 | s2
VCCIO | 21 49 | LDDR1
encdu | 22 48 | GND
D0 | 23 47 | ~PIN002
RESERVED | 24 46 | D1
seg_g | 25 45 | seg_a
GND | 26 44 | seg-f
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
s s s G V S D G V D D G D D D s V
e e e W C W 7 N C 2 3 N 4 5 6 e C
g g g C D C D g C
_ _ _ I I _ I
e c b O N d O
T
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\xyq\maxplus\sy4\alu8.rpt
alu8
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 16/16(100%) 8/ 8(100%) 0/16( 0%) 29/36( 80%)
B: LC17 - LC32 16/16(100%) 8/ 8(100%) 0/16( 0%) 17/36( 47%)
C: LC33 - LC48 16/16(100%) 7/ 8( 87%) 10/16( 62%) 30/36( 83%)
D: LC49 - LC64 15/16( 93%) 8/ 8(100%) 14/16( 87%) 30/36( 83%)
E: LC65 - LC80 14/16( 87%) 7/ 8( 87%) 10/16( 62%) 32/36( 88%)
F: LC81 - LC96 16/16(100%) 1/ 8( 12%) 15/16( 93%) 31/36( 86%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 39/48 ( 81%)
Total logic cells used: 93/96 ( 96%)
Total shareable expanders used: 40/96 ( 41%)
Total Turbo logic cells used: 93/96 ( 96%)
Total shareable expanders not available (n/a): 9/96 ( 9%)
Average fan-in: 5.52
Total fan-in: 514
Total input pins required: 18
Total output pins required: 15
Total bidirectional pins required: 8
Total logic cells required: 93
Total flipflops required: 44
Total product terms required: 305
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 40
Synthesized logic cells: 0/ 96 ( 0%)
Device-Specific Information: e:\xyq\maxplus\sy4\alu8.rpt
alu8
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
13 (1) (A) INPUT 0 0 0 0 0 9 0 ALU_BUS
5 (14) (A) INPUT 0 0 0 0 0 0 8 cir
18 (25) (B) INPUT 0 0 0 0 0 4 0 cir_181
67 - - INPUT G 0 0 0 0 0 0 0 clk
4 (16) (A) INPUT 0 0 0 0 0 1 8 CN
19 (24) (B) INPUT 0 0 0 0 0 0 32 cp_t
23 17 B BIDIR 0 0 0 4 4 0 4 D0
46 65 E BIDIR 0 0 0 4 4 0 4 D1
36 49 D BIDIR 0 0 0 4 4 0 4 D2
37 51 D BIDIR 0 0 0 4 4 0 4 D3
39 53 D BIDIR 0 0 0 4 4 0 4 D4
40 56 D BIDIR 0 0 0 4 4 0 4 D5
41 57 D BIDIR 0 0 0 4 4 0 4 D6
33 33 C BIDIR 0 0 0 4 4 0 4 D7
22 (19) (B) INPUT 0 0 0 0 0 0 4 encdu
20 (21) (B) INPUT 0 0 0 0 0 4 0 en_181
49 (69) (E) INPUT 0 0 0 0 0 0 8 LDDR1
7 (12) (A) INPUT 0 0 0 0 0 0 8 LDDR2
14 (32) (B) INPUT 0 0 0 0 0 0 8 LDR4
17 (27) (B) INPUT 0 0 0 0 0 0 8 LDR5
15 (29) (B) INPUT 0 0 0 0 0 0 8 M
68 - - INPUT G s 0 0 0 0 0 0 0 ~PIN001
12 (4) (A) INPUT 0 0 0 0 0 9 0 R4_BUS
10 (6) (A) INPUT 0 0 0 0 0 9 0 R5_BUS
9 (8) (A) INPUT 0 0 0 0 0 9 0 scan_clk
8 (9) (A) INPUT 0 0 0 0 0 9 0 SW_BUS
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\xyq\maxplus\sy4\alu8.rpt
alu8
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
60 88 F OUTPUT t 6 0 1 1 16 0 0 CN4
23 17 B TRI t 0 0 0 4 4 0 4 D0
46 65 E TRI t 0 0 0 4 4 0 4 D1
36 49 D TRI t 0 0 0 4 4 0 4 D2
37 51 D TRI t 0 0 0 4 4 0 4 D3
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