📄 shiyan3jibengai.rpt
字号:
21 - - D -- TRI 0 1 0 2 d0
17 - - D -- TRI 0 1 0 2 d1
88 - - D -- TRI 0 1 0 2 d2
19 - - D -- TRI 0 1 0 2 d3
18 - - D -- TRI 0 1 0 2 d4
20 - - D -- TRI 0 1 0 2 d5
23 - - D -- TRI 0 1 0 2 d6
22 - - D -- TRI 0 1 0 2 d7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\shiyan3\shiyan3jibengai.rpt
shiyan3jibengai
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 1 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:50|altram:sram|segment0_0
- - 2 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:50|altram:sram|segment0_1
- - 7 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:50|altram:sram|segment0_2
- - 3 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:50|altram:sram|segment0_3
- - 4 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:50|altram:sram|segment0_4
- - 8 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:50|altram:sram|segment0_5
- - 5 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:50|altram:sram|segment0_6
- - 6 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:50|altram:sram|segment0_7
- 1 - D 11 AND2 3 0 0 8 |LPM_RAM_IO:50|:91
- 2 - D 12 AND2 2 0 0 8 :27
- 6 - D 01 AND2 2 0 0 8 :32
- 3 - D 04 DFFE 1 2 0 5 |74161:2|f74161:sub|QA (|74161:2|f74161:sub|:9)
- 2 - D 04 AND2 0 2 0 1 |74161:2|f74161:sub|:84
- 5 - D 04 DFFE 1 3 0 4 |74161:2|f74161:sub|QB (|74161:2|f74161:sub|:87)
- 4 - D 04 AND2 0 3 0 2 |74161:2|f74161:sub|:94
- 7 - D 04 DFFE 1 3 0 3 |74161:2|f74161:sub|QC (|74161:2|f74161:sub|:99)
- 4 - D 06 AND2 0 2 0 2 |74161:2|f74161:sub|:104
- 6 - D 04 DFFE 1 3 0 3 |74161:2|f74161:sub|QD (|74161:2|f74161:sub|:110)
- 1 - D 06 DFFE 1 3 0 3 |74161:3|f74161:sub|QA (|74161:3|f74161:sub|:9)
- 5 - D 06 AND2 0 2 0 2 |74161:3|f74161:sub|:80
- 6 - D 06 AND2 0 2 0 2 |74161:3|f74161:sub|:84
- 2 - D 06 DFFE 1 3 0 3 |74161:3|f74161:sub|QB (|74161:3|f74161:sub|:87)
- 7 - D 06 AND2 0 2 0 1 |74161:3|f74161:sub|:94
- 8 - D 06 DFFE 1 3 0 3 |74161:3|f74161:sub|QC (|74161:3|f74161:sub|:99)
- 3 - D 06 DFFE 1 3 0 2 |74161:3|f74161:sub|QD (|74161:3|f74161:sub|:110)
- 1 - D 19 OR2 4 0 0 0 |74244:4|~1~1~2
- 8 - D 08 OR2 s 3 1 0 1 |74244:4|~1~1~3~2
- 5 - D 08 OR2 2 2 1 0 |74244:4|~1~1~3
- 7 - D 08 OR2 s 3 1 0 1 |74244:4|~6~1~3~2
- 4 - D 08 OR2 2 2 1 0 |74244:4|~6~1~3
- 1 - D 04 OR2 s 3 1 0 1 |74244:4|~10~1~3~2
- 4 - D 11 OR2 2 2 1 0 |74244:4|~10~1~3
- 6 - D 08 OR2 s 3 1 0 1 |74244:4|~11~1~3~2
- 2 - D 08 OR2 2 2 1 0 |74244:4|~11~1~3
- 3 - D 19 OR2 s 3 1 0 1 |74244:4|~26~1~3~2
- 6 - D 19 OR2 2 2 1 0 |74244:4|~26~1~3
- 4 - D 19 OR2 s 3 1 0 1 |74244:4|~27~1~3~2
- 7 - D 19 OR2 2 2 1 0 |74244:4|~27~1~3
- 1 - D 08 OR2 s 3 1 0 1 |74244:4|~31~1~3~2
- 3 - D 08 OR2 2 2 1 0 |74244:4|~31~1~3
- 5 - D 19 OR2 s 3 1 0 1 |74244:4|~36~1~3~2
- 2 - D 19 OR2 2 2 1 0 |74244:4|~36~1~3
- 1 - D 12 DFFE 0 2 1 8 |74273:5|Q8 (|74273:5|:12)
- 3 - D 12 DFFE 0 2 1 8 |74273:5|Q7 (|74273:5|:13)
- 4 - D 12 DFFE 0 2 1 8 |74273:5|Q6 (|74273:5|:14)
- 8 - D 19 DFFE 0 2 1 8 |74273:5|Q5 (|74273:5|:15)
- 8 - D 12 DFFE 0 2 1 8 |74273:5|Q4 (|74273:5|:16)
- 8 - D 04 DFFE 0 2 1 8 |74273:5|Q3 (|74273:5|:17)
- 7 - D 12 DFFE 0 2 1 8 |74273:5|Q2 (|74273:5|:18)
- 6 - D 12 DFFE 0 2 1 8 |74273:5|Q1 (|74273:5|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\shiyan3\shiyan3jibengai.rpt
shiyan3jibengai
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 30/ 96( 31%) 23/ 48( 47%) 6/ 48( 12%) 0/16( 0%) 0/16( 0%) 8/16( 50%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\shiyan3\shiyan3jibengai.rpt
shiyan3jibengai
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 8 :27
LCELL 8 :32
Device-Specific Information: e:\shiyan3\shiyan3jibengai.rpt
shiyan3jibengai
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 161clr
Device-Specific Information: e:\shiyan3\shiyan3jibengai.rpt
shiyan3jibengai
** EQUATIONS **
clk_cdu : INPUT;
cp161ldar : INPUT;
inputd0 : INPUT;
inputd1 : INPUT;
inputd2 : INPUT;
inputd3 : INPUT;
inputd4 : INPUT;
inputd5 : INPUT;
inputd6 : INPUT;
inputd7 : INPUT;
LDAR : INPUT;
MEMENAB : INPUT;
pc_bus : INPUT;
RD : INPUT;
sw_bus : INPUT;
WE : INPUT;
161clr : INPUT;
161load : INPUT;
161pc : INPUT;
-- Node name is 'adr0'
-- Equation name is 'adr0', type is output
adr0 = _LC6_D12;
-- Node name is 'adr1'
-- Equation name is 'adr1', type is output
adr1 = _LC7_D12;
-- Node name is 'adr2'
-- Equation name is 'adr2', type is output
adr2 = _LC8_D4;
-- Node name is 'adr3'
-- Equation name is 'adr3', type is output
adr3 = _LC8_D12;
-- Node name is 'adr4'
-- Equation name is 'adr4', type is output
adr4 = _LC8_D19;
-- Node name is 'adr5'
-- Equation name is 'adr5', type is output
adr5 = _LC4_D12;
-- Node name is 'adr6'
-- Equation name is 'adr6', type is output
adr6 = _LC3_D12;
-- Node name is 'adr7'
-- Equation name is 'adr7', type is output
adr7 = _LC1_D12;
-- Node name is 'd0'
-- Equation name is 'd0', type is bidir
d0 = TRI(_LC5_D8, _LC1_D19);
-- Node name is 'd1'
-- Equation name is 'd1', type is bidir
d1 = TRI(_LC4_D8, _LC1_D19);
-- Node name is 'd2'
-- Equation name is 'd2', type is bidir
d2 = TRI(_LC4_D11, _LC1_D19);
-- Node name is 'd3'
-- Equation name is 'd3', type is bidir
d3 = TRI(_LC2_D8, _LC1_D19);
-- Node name is 'd4'
-- Equation name is 'd4', type is bidir
d4 = TRI(_LC2_D19, _LC1_D19);
-- Node name is 'd5'
-- Equation name is 'd5', type is bidir
d5 = TRI(_LC3_D8, _LC1_D19);
-- Node name is 'd6'
-- Equation name is 'd6', type is bidir
d6 = TRI(_LC7_D19, _LC1_D19);
-- Node name is 'd7'
-- Equation name is 'd7', type is bidir
d7 = TRI(_LC6_D19, _LC1_D19);
-- Node name is '|LPM_RAM_IO:50|:91' from file "lpm_ram_io.tdf" line 187, column 27
-- Equation name is '_LC1_D11', type is buried
_LC1_D11 = LCELL( _EQ001);
_EQ001 = MEMENAB & !RD & WE;
-- Node name is '|74161:2|f74161:sub|:9' = '|74161:2|f74161:sub|QA'
-- Equation name is '_LC3_D4', type is buried
_LC3_D4 = DFFE( _EQ002, _LC6_D1, GLOBAL( 161clr), VCC, VCC);
_EQ002 = d0 & !161load
# !_LC3_D4 & 161load;
-- Node name is '|74161:2|f74161:sub|:87' = '|74161:2|f74161:sub|QB'
-- Equation name is '_LC5_D4', type is buried
_LC5_D4 = DFFE( _EQ003, _LC6_D1, GLOBAL( 161clr), VCC, VCC);
_EQ003 = d1 & !161load
# _LC3_D4 & !_LC5_D4 & 161load
# !_LC3_D4 & _LC5_D4 & 161load;
-- Node name is '|74161:2|f74161:sub|:99' = '|74161:2|f74161:sub|QC'
-- Equation name is '_LC7_D4', type is buried
_LC7_D4 = DFFE( _EQ004, _LC6_D1, GLOBAL( 161clr), VCC, VCC);
_EQ004 = d2 & !161load
# !_LC2_D4 & _LC7_D4 & 161load
# _LC2_D4 & !_LC7_D4 & 161load;
-- Node name is '|74161:2|f74161:sub|:110' = '|74161:2|f74161:sub|QD'
-- Equation name is '_LC6_D4', type is buried
_LC6_D4 = DFFE( _EQ005, _LC6_D1, GLOBAL( 161clr), VCC, VCC);
_EQ005 = d3 & !161load
# !_LC4_D4 & _LC6_D4 & 161load
# _LC4_D4 & !_LC6_D4 & 161load;
-- Node name is '|74161:2|f74161:sub|:84'
-- Equation name is '_LC2_D4', type is buried
_LC2_D4 = LCELL( _EQ006);
_EQ006 = _LC3_D4 & _LC5_D4;
-- Node name is '|74161:2|f74161:sub|:94'
-- Equation name is '_LC4_D4', type is buried
_LC4_D4 = LCELL( _EQ007);
_EQ007 = _LC3_D4 & _LC5_D4 & _LC7_D4;
-- Node name is '|74161:2|f74161:sub|:104'
-- Equation name is '_LC4_D6', type is buried
_LC4_D6 = LCELL( _EQ008);
_EQ008 = _LC4_D4 & _LC6_D4;
-- Node name is '|74161:3|f74161:sub|:9' = '|74161:3|f74161:sub|QA'
-- Equation name is '_LC1_D6', type is buried
_LC1_D6 = DFFE( _EQ009, _LC6_D1, GLOBAL( 161clr), VCC, VCC);
_EQ009 = d4 & !161load
# _LC1_D6 & !_LC4_D6 & 161load
# !_LC1_D6 & _LC4_D6 & 161load;
-- Node name is '|74161:3|f74161:sub|:87' = '|74161:3|f74161:sub|QB'
-- Equation name is '_LC2_D6', type is buried
_LC2_D6 = DFFE( _EQ010, _LC6_D1, GLOBAL( 161clr), VCC, VCC);
_EQ010 = d5 & !161load
# _LC2_D6 & !_LC5_D6 & 161load
# !_LC2_D6 & _LC5_D6 & 161load;
-- Node name is '|74161:3|f74161:sub|:99' = '|74161:3|f74161:sub|QC'
-- Equation name is '_LC8_D6', type is buried
_LC8_D6 = DFFE( _EQ011, _LC6_D1, GLOBAL( 161clr), VCC, VCC);
_EQ011 = d6 & !161load
# !_LC6_D6 & _LC8_D6 & 161load
# _LC6_D6 & !_LC8_D6 & 161load;
-- Node name is '|74161:3|f74161:sub|:110' = '|74161:3|f74161:sub|QD'
-- Equation name is '_LC3_D6', type is buried
_LC3_D6 = DFFE( _EQ012, _LC6_D1, GLOBAL( 161clr), VCC, VCC);
_EQ012 = d7 & !161load
# _LC3_D6 & !_LC7_D6 & 161load
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