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📄 yunsuan.rpt

📁 用verilog语言写的拔河游戏机
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_LC067   = LCELL( _EQ037 $  VCC);
  _EQ037 =  _LC024 &  _LC032 &  s3
         # !_LC024 &  _LC032 &  s2;

-- Node name is '|74181:149|:41' 
-- Equation name is '_LC066', type is buried 
_LC066   = LCELL( _EQ038 $ !_LC030);
  _EQ038 =  _LC020 & !_LC030 &  s0
         # !_LC020 & !_LC030 &  s1;

-- Node name is '|74181:149|:42' 
-- Equation name is '_LC065', type is buried 
_LC065   = LCELL( _EQ039 $  VCC);
  _EQ039 =  _LC020 &  _LC030 &  s3
         # !_LC020 &  _LC030 &  s2;

-- Node name is '|74181:149|:49' 
-- Equation name is '_LC074', type is buried 
_LC074   = LCELL( _EQ040 $  VCC);
  _EQ040 =  _LC021 &  _LC028 &  s3
         # !_LC021 &  _LC028 &  s2;

-- Node name is '|74181:149|:50' 
-- Equation name is '_LC071', type is buried 
_LC071   = LCELL( _EQ041 $ !_LC028);
  _EQ041 =  _LC021 & !_LC028 &  s0
         # !_LC021 & !_LC028 &  s1;

-- Node name is '|74181:149|:76' 
-- Equation name is '_LC093', type is buried 
_LC093   = LCELL( _EQ042 $  VCC);
  _EQ042 =  CN &  _LC065 &  _LC067 &  _LC075 & !M
         #  _LC065 &  _LC067 &  _LC068 & !M
         #  _LC065 &  _LC080 & !M
         #  _LC066 & !M;

-- Node name is '|74181:149|:88' 
-- Equation name is '_LC091', type is buried 
_LC091   = LCELL( _EQ043 $  VCC);
  _EQ043 =  CN &  _LC075 & !M
         #  _LC068 & !M;

-- Node name is '|74181:149|:89' 
-- Equation name is '_LC089', type is buried 
_LC089   = LCELL( _EQ044 $  VCC);
  _EQ044 =  CN &  _LC067 &  _LC075 & !M
         #  _LC067 &  _LC068 & !M
         #  _LC080 & !M;

-- Node name is '|74273:146|:19' = '|74273:146|Q1' 
-- Equation name is '_LC022', type is buried 
_LC022   = DFFE( D0 $  GND,  _EQ045,  VCC,  VCC,  VCC);
  _EQ045 = !cp_t &  LDDR2;

-- Node name is '|74273:146|:18' = '|74273:146|Q2' 
-- Equation name is '_LC024', type is buried 
_LC024   = DFFE( D1 $  GND,  _EQ046,  VCC,  VCC,  VCC);
  _EQ046 = !cp_t &  LDDR2;

-- Node name is '|74273:146|:17' = '|74273:146|Q3' 
-- Equation name is '_LC020', type is buried 
_LC020   = DFFE( D2 $  GND,  _EQ047,  VCC,  VCC,  VCC);
  _EQ047 = !cp_t &  LDDR2;

-- Node name is '|74273:146|:16' = '|74273:146|Q4' 
-- Equation name is '_LC021', type is buried 
_LC021   = DFFE( D3 $  GND,  _EQ048,  VCC,  VCC,  VCC);
  _EQ048 = !cp_t &  LDDR2;

-- Node name is '|74273:146|:15' = '|74273:146|Q5' 
-- Equation name is '_LC034', type is buried 
_LC034   = DFFE( D4 $  GND,  _EQ049,  VCC,  VCC,  VCC);
  _EQ049 = !cp_t &  LDDR2;

-- Node name is '|74273:146|:14' = '|74273:146|Q6' 
-- Equation name is '_LC035', type is buried 
_LC035   = DFFE( D5 $  GND,  _EQ050,  VCC,  VCC,  VCC);
  _EQ050 = !cp_t &  LDDR2;

-- Node name is '|74273:146|:13' = '|74273:146|Q7' 
-- Equation name is '_LC041', type is buried 
_LC041   = DFFE( D6 $  GND,  _EQ051,  VCC,  VCC,  VCC);
  _EQ051 = !cp_t &  LDDR2;

-- Node name is '|74273:146|:12' = '|74273:146|Q8' 
-- Equation name is '_LC040', type is buried 
_LC040   = DFFE( D7 $  GND,  _EQ052,  VCC,  VCC,  VCC);
  _EQ052 = !cp_t &  LDDR2;

-- Node name is '|74273:147|:19' = '|74273:147|Q1' 
-- Equation name is '_LC029', type is buried 
_LC029   = DFFE( D0 $  GND,  _EQ053,  VCC,  VCC,  VCC);
  _EQ053 = !cp_t &  LDDR1;

-- Node name is '|74273:147|:18' = '|74273:147|Q2' 
-- Equation name is '_LC032', type is buried 
_LC032   = DFFE( D1 $  GND,  _EQ054,  VCC,  VCC,  VCC);
  _EQ054 = !cp_t &  LDDR1;

-- Node name is '|74273:147|:17' = '|74273:147|Q3' 
-- Equation name is '_LC030', type is buried 
_LC030   = DFFE( D2 $  GND,  _EQ055,  VCC,  VCC,  VCC);
  _EQ055 = !cp_t &  LDDR1;

-- Node name is '|74273:147|:16' = '|74273:147|Q4' 
-- Equation name is '_LC028', type is buried 
_LC028   = DFFE( D3 $  GND,  _EQ056,  VCC,  VCC,  VCC);
  _EQ056 = !cp_t &  LDDR1;

-- Node name is '|74273:147|:15' = '|74273:147|Q5' 
-- Equation name is '_LC046', type is buried 
_LC046   = DFFE( D4 $  GND,  _EQ057,  VCC,  VCC,  VCC);
  _EQ057 = !cp_t &  LDDR1;

-- Node name is '|74273:147|:14' = '|74273:147|Q6' 
-- Equation name is '_LC039', type is buried 
_LC039   = DFFE( D5 $  GND,  _EQ058,  VCC,  VCC,  VCC);
  _EQ058 = !cp_t &  LDDR1;

-- Node name is '|74273:147|:13' = '|74273:147|Q7' 
-- Equation name is '_LC047', type is buried 
_LC047   = DFFE( D6 $  GND,  _EQ059,  VCC,  VCC,  VCC);
  _EQ059 = !cp_t &  LDDR1;

-- Node name is '|74273:147|:12' = '|74273:147|Q8' 
-- Equation name is '_LC048', type is buried 
_LC048   = DFFE( D7 $  GND,  _EQ060,  VCC,  VCC,  VCC);
  _EQ060 = !cp_t &  LDDR1;

-- Node name is '|74374:144|:13' 
-- Equation name is '_LC023', type is buried 
_LC023   = DFFE( D0 $  GND,  _EQ061,  VCC,  VCC,  VCC);
  _EQ061 = !cp_t &  LDR5;

-- Node name is '|74374:144|:14' 
-- Equation name is '_LC019', type is buried 
_LC019   = DFFE( D1 $  GND,  _EQ062,  VCC,  VCC,  VCC);
  _EQ062 = !cp_t &  LDR5;

-- Node name is '|74374:144|:15' 
-- Equation name is '_LC018', type is buried 
_LC018   = DFFE( D2 $  GND,  _EQ063,  VCC,  VCC,  VCC);
  _EQ063 = !cp_t &  LDR5;

-- Node name is '|74374:144|:16' 
-- Equation name is '_LC017', type is buried 
_LC017   = DFFE( D3 $  GND,  _EQ064,  VCC,  VCC,  VCC);
  _EQ064 = !cp_t &  LDR5;

-- Node name is '|74374:144|:17' 
-- Equation name is '_LC042', type is buried 
_LC042   = DFFE( D4 $  GND,  _EQ065,  VCC,  VCC,  VCC);
  _EQ065 = !cp_t &  LDR5;

-- Node name is '|74374:144|:18' 
-- Equation name is '_LC043', type is buried 
_LC043   = DFFE( D5 $  GND,  _EQ066,  VCC,  VCC,  VCC);
  _EQ066 = !cp_t &  LDR5;

-- Node name is '|74374:144|:19' 
-- Equation name is '_LC044', type is buried 
_LC044   = DFFE( D6 $  GND,  _EQ067,  VCC,  VCC,  VCC);
  _EQ067 = !cp_t &  LDR5;

-- Node name is '|74374:144|:20' 
-- Equation name is '_LC045', type is buried 
_LC045   = DFFE( D7 $  GND,  _EQ068,  VCC,  VCC,  VCC);
  _EQ068 = !cp_t &  LDR5;

-- Node name is '|74374:145|:13' 
-- Equation name is '_LC025', type is buried 
_LC025   = DFFE( D0 $  GND,  _EQ069,  VCC,  VCC,  VCC);
  _EQ069 = !cp_t &  LDR4;

-- Node name is '|74374:145|:14' 
-- Equation name is '_LC026', type is buried 
_LC026   = DFFE( D1 $  GND,  _EQ070,  VCC,  VCC,  VCC);
  _EQ070 = !cp_t &  LDR4;

-- Node name is '|74374:145|:15' 
-- Equation name is '_LC027', type is buried 
_LC027   = DFFE( D2 $  GND,  _EQ071,  VCC,  VCC,  VCC);
  _EQ071 = !cp_t &  LDR4;

-- Node name is '|74374:145|:16' 
-- Equation name is '_LC031', type is buried 
_LC031   = DFFE( D3 $  GND,  _EQ072,  VCC,  VCC,  VCC);
  _EQ072 = !cp_t &  LDR4;

-- Node name is '|74374:145|:17' 
-- Equation name is '_LC033', type is buried 
_LC033   = DFFE( D4 $  GND,  _EQ073,  VCC,  VCC,  VCC);
  _EQ073 = !cp_t &  LDR4;

-- Node name is '|74374:145|:18' 
-- Equation name is '_LC036', type is buried 
_LC036   = DFFE( D5 $  GND,  _EQ074,  VCC,  VCC,  VCC);
  _EQ074 = !cp_t &  LDR4;

-- Node name is '|74374:145|:19' 
-- Equation name is '_LC037', type is buried 
_LC037   = DFFE( D6 $  GND,  _EQ075,  VCC,  VCC,  VCC);
  _EQ075 = !cp_t &  LDR4;

-- Node name is '|74374:145|:20' 
-- Equation name is '_LC038', type is buried 
_LC038   = DFFE( D7 $  GND,  _EQ076,  VCC,  VCC,  VCC);
  _EQ076 = !cp_t &  LDR4;

-- Node name is '|74244:150|~26~1~2~2' 
-- Equation name is '|74244:150|~26~1~2~2', type is output 
 ~PIN002 = LCELL( _EQ077 $  GND);
  _EQ077 =  ALU_BUS &  R4_BUS &  R5_BUS &  SW_BUS;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                             e:\xyq\maxplus\xyq\yunsuan.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,316K

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