📄 yunsuan.rpt
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Project Information e:\xyq\maxplus\xyq\yunsuan.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 03/22/2008 20:58:23
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
yunsuan EPM7096LC68-7 24 2 8 72 21 75 %
User Pins: 23 1 8
Project Information e:\xyq\maxplus\xyq\yunsuan.rpt
** MULTIPLE PIN CONNECTIONS **
For node name '|74244:150|~26~1~2~3' (Same as node '~PIN001')
For node name '|74244:150|~26~1~2~2' (Same as node '~PIN002')
Connect: {yunsuan@68, yunsuan@49}
Project Information e:\xyq\maxplus\xyq\yunsuan.rpt
** FILE HIERARCHY **
|74244:150|
|74244:151|
|74181:148|
|74181:149|
|74273:146|
|74273:147|
|74374:144|
|74374:145|
Device-Specific Information: e:\xyq\maxplus\xyq\yunsuan.rpt
yunsuan
***** Logic for device 'yunsuan' compiled without errors.
Device: EPM7096LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
R R R R
A E ~ E E E
L S S V P S S S
L U W E C I E E V E
D _ _ R C N R R C R
D B B G V I G G 0 G G V V C i V
R U U N E s N N N 0 N N E E I n E
2 S S D D 3 T D D 1 D D D D O 4 D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
LDR4 | 10 60 | RESERVED
VCCIO | 11 59 | RESERVED
M | 12 58 | GND
LDR5 | 13 57 | RESERVED
s1 | 14 56 | CN4
LDDR1 | 15 55 | RESERVED
GND | 16 54 | in6
R4_BUS | 17 53 | VCCIO
RESERVED | 18 EPM7096LC68-7 52 | RESERVED
RESERVED | 19 51 | RESERVED
CN | 20 50 | in5
VCCIO | 21 49 | ~PIN002
cp_t | 22 48 | GND
s2 | 23 47 | R5_BUS
RESERVED | 24 46 | RESERVED
s0 | 25 45 | D4
GND | 26 44 | D3
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
i i i i V R i G V D D G D D D D V
n n n n C E n N C 2 5 N 1 0 6 7 C
7 2 1 0 C S 3 D C D C
I E I I
O R N O
V T
E
D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\xyq\maxplus\xyq\yunsuan.rpt
yunsuan
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 7/ 8( 87%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 16/16(100%) 6/ 8( 75%) 0/16( 0%) 9/36( 25%)
C: LC33 - LC48 16/16(100%) 6/ 8( 75%) 0/16( 0%) 9/36( 25%)
D: LC49 - LC64 8/16( 50%) 8/ 8(100%) 0/16( 0%) 36/36(100%)
E: LC65 - LC80 16/16(100%) 4/ 8( 50%) 10/16( 62%) 33/36( 91%)
F: LC81 - LC96 16/16(100%) 2/ 8( 25%) 15/16( 93%) 31/36( 86%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 33/48 ( 68%)
Total logic cells used: 72/96 ( 75%)
Total shareable expanders used: 21/96 ( 21%)
Total Turbo logic cells used: 72/96 ( 75%)
Total shareable expanders not available (n/a): 4/96 ( 4%)
Average fan-in: 5.15
Total fan-in: 371
Total input pins required: 24
Total output pins required: 2
Total bidirectional pins required: 8
Total logic cells required: 72
Total flipflops required: 32
Total product terms required: 217
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 21
Synthesized logic cells: 0/ 96 ( 0%)
Device-Specific Information: e:\xyq\maxplus\xyq\yunsuan.rpt
yunsuan
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
8 (9) (A) INPUT 0 0 0 0 0 9 0 ALU_BUS
20 (21) (B) INPUT 0 0 0 0 0 1 8 CN
22 (19) (B) INPUT 0 0 0 0 0 0 32 cp_t
40 56 D BIDIR 0 0 0 5 3 0 4 D0
39 53 D BIDIR 0 0 0 5 3 0 4 D1
36 49 D BIDIR 0 0 0 5 3 0 4 D2
44 61 D BIDIR 0 0 0 5 3 0 4 D3
45 64 D BIDIR 0 0 0 5 3 0 4 D4
37 51 D BIDIR 0 0 0 5 3 0 4 D5
41 57 D BIDIR 0 0 0 5 3 0 4 D6
42 59 D BIDIR 0 0 0 5 3 0 4 D7
30 (37) (C) INPUT 0 0 0 0 0 1 0 in0
29 (40) (C) INPUT 0 0 0 0 0 1 0 in1
28 (41) (C) INPUT 0 0 0 0 0 1 0 in2
33 (33) (C) INPUT 0 0 0 0 0 1 0 in3
62 (92) (F) INPUT 0 0 0 0 0 1 0 in4
50 (72) (E) INPUT 0 0 0 0 0 1 0 in5
54 (77) (E) INPUT 0 0 0 0 0 1 0 in6
27 (43) (C) INPUT 0 0 0 0 0 1 0 in7
15 (29) (B) INPUT 0 0 0 0 0 0 8 LDDR1
9 (8) (A) INPUT 0 0 0 0 0 0 8 LDDR2
10 (6) (A) INPUT 0 0 0 0 0 0 8 LDR4
13 (1) (A) INPUT 0 0 0 0 0 0 8 LDR5
12 (4) (A) INPUT 0 0 0 0 0 0 8 M
68 - - INPUT G s 0 0 0 0 0 0 0 ~PIN001
17 (27) (B) INPUT 0 0 0 0 0 9 0 R4_BUS
47 (67) (E) INPUT 0 0 0 0 0 9 0 R5_BUS
7 (12) (A) INPUT 0 0 0 0 0 9 0 SW_BUS
25 (45) (C) INPUT 0 0 0 0 0 0 8 s0
14 (32) (B) INPUT 0 0 0 0 0 0 8 s1
23 (17) (B) INPUT 0 0 0 0 0 0 14 s2
4 (16) (A) INPUT 0 0 0 0 0 0 14 s3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\xyq\maxplus\xyq\yunsuan.rpt
yunsuan
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
56 81 F OUTPUT t 6 0 1 1 16 0 0 CN4
40 56 D TRI t 0 0 0 5 3 0 4 D0
39 53 D TRI t 0 0 0 5 3 0 4 D1
36 49 D TRI t 0 0 0 5 3 0 4 D2
44 61 D TRI t 0 0 0 5 3 0 4 D3
45 64 D TRI t 0 0 0 5 3 0 4 D4
37 51 D TRI t 0 0 0 5 3 0 4 D5
41 57 D TRI t 0 0 0 5 3 0 4 D6
42 59 D TRI t 0 0 0 5 3 0 4 D7
49 69 E OUTPUT t 0 0 0 4 0 0 0 ~PIN002
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\xyq\maxplus\xyq\yunsuan.rpt
yunsuan
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 70 E SOFT t 0 0 0 2 2 1 4 |74181:148|:37
(51) 73 E SOFT t 0 0 0 2 2 1 4 |74181:148|:38
(57) 84 F SOFT t 0 0 0 2 2 1 3 |74181:148|:39
- 82 F SOFT t 0 0 0 2 2 1 3 |74181:148|:40
- 83 F SOFT t 0 0 0 2 2 1 2 |74181:148|:41
- 90 F SOFT t 0 0 0 2 2 1 2 |74181:148|:42
(62) 92 F SOFT t 0 0 0 2 2 1 1 |74181:148|:49
- 87 F SOFT t 0 0 0 2 2 1 1 |74181:148|:50
(65) 96 F SOFT t 5 0 1 2 14 0 1 |74181:148|:76
- 95 F SOFT t 0 0 0 2 5 1 0 |74181:148|F3N (|74181:148|:84)
(59) 86 F SOFT t 0 0 0 2 5 1 0 |74181:148|F2N (|74181:148|:85)
(60) 88 F SOFT t 0 0 0 2 5 1 0 |74181:148|F1N (|74181:148|:86)
- 78 E SOFT t 7 0 0 2 10 1 0 |74181:148|F0N (|74181:148|:87)
(50) 72 E SOFT t 3 0 1 2 10 0 1 |74181:148|:88
(64) 94 F SOFT t 4 0 1 2 12 0 1 |74181:148|:89
- 68 E SOFT t 0 0 0 2 2 1 8 |74181:149|:37
(52) 75 E SOFT t 0 0 0 2 2 1 8 |74181:149|:38
(55) 80 E SOFT t 0 0 0 2 2 1 7 |74181:149|:39
(47) 67 E SOFT t 0 0 0 2 2 1 7 |74181:149|:40
- 66 E SOFT t 0 0 0 2 2 1 6 |74181:149|:41
(46) 65 E SOFT t 0 0 0 2 2 1 6 |74181:149|:42
- 74 E SOFT t 0 0 0 2 2 1 5 |74181:149|:49
- 71 E SOFT t 0 0 0 2 2 1 5 |74181:149|:50
- 93 F SOFT t 0 0 0 2 6 0 1 |74181:149|:76
- 79 E SOFT t 0 0 0 2 5 1 0 |74181:149|F3N (|74181:149|:84)
(54) 77 E SOFT t 0 0 0 2 5 1 0 |74181:149|F2N (|74181:149|:85)
- 76 E SOFT t 0 0 0 2 5 1 0 |74181:149|F1N (|74181:149|:86)
- 85 F SOFT t 0 0 0 2 2 1 0 |74181:149|F0N (|74181:149|:87)
- 91 F SOFT t 0 0 0 2 2 0 1 |74181:149|:88
(61) 89 F SOFT t 0 0 0 2 4 0 1 |74181:149|:89
(29) 40 C DFFE t 0 0 0 2 1 0 3 |74273:146|Q8 (|74273:146|:12)
(28) 41 C DFFE t 0 0 0 2 1 0 3 |74273:146|Q7 (|74273:146|:13)
(32) 35 C DFFE t 0 0 0 2 1 0 3 |74273:146|Q6 (|74273:146|:14)
- 34 C DFFE t 0 0 0 2 1 0 2 |74273:146|Q5 (|74273:146|:15)
(20) 21 B DFFE t 0 0 0 2 1 0 3 |74273:146|Q4 (|74273:146|:16)
- 20 B DFFE t 0 0 0 2 1 0 3 |74273:146|Q3 (|74273:146|:17)
(19) 24 B DFFE t 0 0 0 2 1 0 3 |74273:146|Q2 (|74273:146|:18)
- 22 B DFFE t 0 0 0 2 1 0 2 |74273:146|Q1 (|74273:146|:19)
(24) 48 C DFFE t 0 0 0 2 1 0 3 |74273:147|Q8 (|74273:147|:12)
- 47 C DFFE t 0 0 0 2 1 0 3 |74273:147|Q7 (|74273:147|:13)
- 39 C DFFE t 0 0 0 2 1 0 3 |74273:147|Q6 (|74273:147|:14)
- 46 C DFFE t 0 0 0 2 1 0 2 |74273:147|Q5 (|74273:147|:15)
- 28 B DFFE t 0 0 0 2 1 0 3 |74273:147|Q4 (|74273:147|:16)
- 30 B DFFE t 0 0 0 2 1 0 3 |74273:147|Q3 (|74273:147|:17)
(14) 32 B DFFE t 0 0 0 2 1 0 3 |74273:147|Q2 (|74273:147|:18)
(15) 29 B DFFE t 0 0 0 2 1 0 2 |74273:147|Q1 (|74273:147|:19)
- 23 B DFFE t 0 0 0 2 1 1 0 |74374:144|:13
(22) 19 B DFFE t 0 0 0 2 1 1 0 |74374:144|:14
- 18 B DFFE t 0 0 0 2 1 1 0 |74374:144|:15
(23) 17 B DFFE t 0 0 0 2 1 1 0 |74374:144|:16
- 42 C DFFE t 0 0 0 2 1 1 0 |74374:144|:17
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