scan.v

用verilog语言写的拔河游戏机

module scan(scan_clk,in,CLR,seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g,Q1,Q0);
output Q1,Q0;
output seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g;
//input in0,in1,in2,in3,in4,in5,in6,in7;
input scan_clk,CLR;
input [7:0]in;
reg [6:0]dec;
reg Q1,Q0;
reg [3:0]indec;
assign {seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g}=dec;
//assign in={in7,in6,in5,in4,in3,in2,in1,in0};

always @(posedge scan_clk or negedge CLR)
begin
if(!CLR) {Q1,Q0}<=0;
else 
if({Q1,Q0}==2'b10)
{Q1,Q0}<=2'b01;
else {Q1,Q0}<={Q1,Q0}+1;
end

always @({Q1,Q0})
begin
case({Q1,Q0})
2'b01:indec<=in[3:0];
2'b10:indec<=in[7:4];
default:indec<=2'bx;
endcase
end
/********七段译码器0——F**********/
always @(indec)
begin
case(indec)
4'd0:dec=7'b1111110;
4'd1:dec=7'b0110000;
4'd2:dec=7'b1101101;
4'd3:dec=7'b1111001;
4'd4:dec=7'b0110011;
4'd5:dec=7'b1011011;
4'd6:dec=7'b1011111;
4'd7:dec=7'b1110000;
4'd8:dec=7'b1111111;
4'd9:dec=7'b1110011;
4'd10:dec=7'b1110111;
4'd11:dec=7'b0011111;
4'd12:dec=7'b1001110;
4'd13:dec=7'b0111101;
4'd14:dec=7'b1001111;
4'd15:dec=7'b1000111;
default:dec=7'bx;
endcase
end
endmodule