📄 test_ram.rpt
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-- Equation name is '_LC1_E17', type is buried
!_LC1_E17 = _LC1_E17~NOT;
_LC1_E17~NOT = LCELL( _EQ053);
_EQ053 = !_LC7_B20 & !scan_clk
# !_LC3_B19 & scan_clk
# !_LC3_B19 & !_LC7_B20;
-- Node name is '|saomiao:62|74157:9|:25' = '|saomiao:62|74157:9|Y4'
-- Equation name is '_LC8_B19', type is buried
_LC8_B19 = LCELL( _EQ054);
_EQ054 = _LC2_B19 & !scan_clk
# _LC1_B19 & scan_clk;
-- Node name is '|74161:116|f74161:sub|:9' = '|74161:116|f74161:sub|QA'
-- Equation name is '_LC3_B23', type is buried
_LC3_B23 = DFFE( _EQ055, _LC6_D24, 161clr, VCC, VCC);
_EQ055 = d0 & !161load
# !_LC3_B23 & 161load;
-- Node name is '|74161:116|f74161:sub|:87' = '|74161:116|f74161:sub|QB'
-- Equation name is '_LC2_B23', type is buried
_LC2_B23 = DFFE( _EQ056, _LC6_D24, 161clr, VCC, VCC);
_EQ056 = d1 & !161load
# _LC2_B23 & !_LC3_B23 & 161load
# !_LC2_B23 & _LC3_B23 & 161load;
-- Node name is '|74161:116|f74161:sub|:99' = '|74161:116|f74161:sub|QC'
-- Equation name is '_LC1_B23', type is buried
_LC1_B23 = DFFE( _EQ057, _LC6_D24, 161clr, VCC, VCC);
_EQ057 = d2 & !161load
# _LC1_B23 & !_LC4_B23 & 161load
# !_LC1_B23 & _LC4_B23 & 161load;
-- Node name is '|74161:116|f74161:sub|:110' = '|74161:116|f74161:sub|QD'
-- Equation name is '_LC5_B23', type is buried
_LC5_B23 = DFFE( _EQ058, _LC6_D24, 161clr, VCC, VCC);
_EQ058 = d3 & !161load
# _LC5_B23 & !_LC6_B23 & 161load
# !_LC5_B23 & _LC6_B23 & 161load;
-- Node name is '|74161:116|f74161:sub|:84'
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = LCELL( _EQ059);
_EQ059 = _LC2_B23 & _LC3_B23;
-- Node name is '|74161:116|f74161:sub|:94'
-- Equation name is '_LC6_B23', type is buried
_LC6_B23 = LCELL( _EQ060);
_EQ060 = _LC1_B23 & _LC2_B23 & _LC3_B23;
-- Node name is '|74161:116|f74161:sub|:104'
-- Equation name is '_LC8_B23', type is buried
_LC8_B23 = LCELL( _EQ061);
_EQ061 = _LC1_B23 & _LC2_B23 & _LC3_B23 & _LC5_B23;
-- Node name is '|74161:117|f74161:sub|:9' = '|74161:117|f74161:sub|QA'
-- Equation name is '_LC4_B24', type is buried
_LC4_B24 = DFFE( _EQ062, _LC6_D24, 161clr, VCC, VCC);
_EQ062 = d4 & !161load
# _LC4_B24 & !_LC8_B23 & 161load
# !_LC4_B24 & _LC8_B23 & 161load;
-- Node name is '|74161:117|f74161:sub|:87' = '|74161:117|f74161:sub|QB'
-- Equation name is '_LC6_B24', type is buried
_LC6_B24 = DFFE( _EQ063, _LC6_D24, 161clr, VCC, VCC);
_EQ063 = d5 & !161load
# !_LC5_B24 & _LC6_B24 & 161load
# _LC5_B24 & !_LC6_B24 & 161load;
-- Node name is '|74161:117|f74161:sub|:99' = '|74161:117|f74161:sub|QC'
-- Equation name is '_LC2_B24', type is buried
_LC2_B24 = DFFE( _EQ064, _LC6_D24, 161clr, VCC, VCC);
_EQ064 = d6 & !161load
# _LC2_B24 & !_LC7_B24 & 161load
# !_LC2_B24 & _LC7_B24 & 161load;
-- Node name is '|74161:117|f74161:sub|:110' = '|74161:117|f74161:sub|QD'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = DFFE( _EQ065, _LC6_D24, 161clr, VCC, VCC);
_EQ065 = d7 & !161load
# _LC1_B24 & !_LC8_B24 & 161load
# !_LC1_B24 & _LC8_B24 & 161load;
-- Node name is '|74161:117|f74161:sub|:80'
-- Equation name is '_LC5_B24', type is buried
_LC5_B24 = LCELL( _EQ066);
_EQ066 = _LC4_B24 & _LC8_B23;
-- Node name is '|74161:117|f74161:sub|:84'
-- Equation name is '_LC7_B24', type is buried
_LC7_B24 = LCELL( _EQ067);
_EQ067 = _LC4_B24 & _LC6_B24 & _LC8_B23;
-- Node name is '|74161:117|f74161:sub|:94'
-- Equation name is '_LC8_B24', type is buried
_LC8_B24 = LCELL( _EQ068);
_EQ068 = _LC2_B24 & _LC4_B24 & _LC6_B24 & _LC8_B23;
-- Node name is '|74273:115|:19' = '|74273:115|Q1'
-- Equation name is '_LC5_B8', type is buried
_LC5_B8 = DFFE( d0, _LC3_B8, VCC, VCC, VCC);
-- Node name is '|74273:115|:18' = '|74273:115|Q2'
-- Equation name is '_LC6_B8', type is buried
_LC6_B8 = DFFE( d1, _LC3_B8, VCC, VCC, VCC);
-- Node name is '|74273:115|:17' = '|74273:115|Q3'
-- Equation name is '_LC7_B8', type is buried
_LC7_B8 = DFFE( d2, _LC3_B8, VCC, VCC, VCC);
-- Node name is '|74273:115|:16' = '|74273:115|Q4'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = DFFE( d3, _LC3_B8, VCC, VCC, VCC);
-- Node name is '|74273:115|:15' = '|74273:115|Q5'
-- Equation name is '_LC2_B8', type is buried
_LC2_B8 = DFFE( d4, _LC3_B8, VCC, VCC, VCC);
-- Node name is '|74273:115|:14' = '|74273:115|Q6'
-- Equation name is '_LC5_B5', type is buried
_LC5_B5 = DFFE( d5, _LC3_B8, VCC, VCC, VCC);
-- Node name is '|74273:115|:13' = '|74273:115|Q7'
-- Equation name is '_LC8_B8', type is buried
_LC8_B8 = DFFE( d6, _LC3_B8, VCC, VCC, VCC);
-- Node name is '|74273:115|:12' = '|74273:115|Q8'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = DFFE( d7, _LC3_B8, VCC, VCC, VCC);
-- Node name is ':60'
-- Equation name is '_LC7_B19', type is buried
_LC7_B19 = LCELL( _EQ069);
_EQ069 = _LC2_B19 & _LC4_B20;
-- Node name is ':80'
-- Equation name is '_LC3_B8', type is buried
_LC3_B8 = LCELL( _EQ070);
_EQ070 = !cp161ldar & LDAR;
-- Node name is ':81'
-- Equation name is '_LC6_D24', type is buried
_LC6_D24 = LCELL( _EQ071);
_EQ071 = clk_cdu & 161pc;
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_0' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC4_B', type is memory
_EC4_B = MEMORY_SEGMENT( d0, clk_cdu, VCC, _LC7_B16, VCC, _LC5_B8, _LC6_B8, _LC7_B8, _LC4_B8, _LC2_B8, _LC5_B5, _LC8_B8, _LC1_B8, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_1' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC8_B', type is memory
_EC8_B = MEMORY_SEGMENT( d1, clk_cdu, VCC, _LC7_B16, VCC, _LC5_B8, _LC6_B8, _LC7_B8, _LC4_B8, _LC2_B8, _LC5_B5, _LC8_B8, _LC1_B8, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_2' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC6_B', type is memory
_EC6_B = MEMORY_SEGMENT( d2, clk_cdu, VCC, _LC7_B16, VCC, _LC5_B8, _LC6_B8, _LC7_B8, _LC4_B8, _LC2_B8, _LC5_B5, _LC8_B8, _LC1_B8, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_3' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC5_B', type is memory
_EC5_B = MEMORY_SEGMENT( d3, clk_cdu, VCC, _LC7_B16, VCC, _LC5_B8, _LC6_B8, _LC7_B8, _LC4_B8, _LC2_B8, _LC5_B5, _LC8_B8, _LC1_B8, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_4' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC2_B', type is memory
_EC2_B = MEMORY_SEGMENT( d4, clk_cdu, VCC, _LC7_B16, VCC, _LC5_B8, _LC6_B8, _LC7_B8, _LC4_B8, _LC2_B8, _LC5_B5, _LC8_B8, _LC1_B8, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_5' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC1_B', type is memory
_EC1_B = MEMORY_SEGMENT( d5, clk_cdu, VCC, _LC7_B16, VCC, _LC5_B8, _LC6_B8, _LC7_B8, _LC4_B8, _LC2_B8, _LC5_B5, _LC8_B8, _LC1_B8, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_6' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC3_B', type is memory
_EC3_B = MEMORY_SEGMENT( d6, clk_cdu, VCC, _LC7_B16, VCC, _LC5_B8, _LC6_B8, _LC7_B8, _LC4_B8, _LC2_B8, _LC5_B5, _LC8_B8, _LC1_B8, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_7' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC7_B', type is memory
_EC7_B = MEMORY_SEGMENT( d7, clk_cdu, VCC, _LC7_B16, VCC, _LC5_B8, _LC6_B8, _LC7_B8, _LC4_B8, _LC2_B8, _LC5_B5, _LC8_B8, _LC1_B8, VCC, VCC, VCC,);
Project Information e:\xyq\maxplus\sy4\test_ram.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,982K
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