test_ram.rpt

用verilog语言写的拔河游戏机

16:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
17:      5/24( 20%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
18:      6/24( 25%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
19:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      4/24( 16%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                   e:\xyq\maxplus\sy4\test_ram.rpt
test_ram

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       17         clk_cdu
LCELL        8         :80
LCELL        8         :81


Device-Specific Information:                   e:\xyq\maxplus\sy4\test_ram.rpt
test_ram

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT        8         161clr


Device-Specific Information:                   e:\xyq\maxplus\sy4\test_ram.rpt
test_ram

** EQUATIONS **

clk_cdu  : INPUT;
clr_cdu  : INPUT;
cp161ldar : INPUT;
en_cdu   : INPUT;
LDAR     : INPUT;
MEMENAB  : INPUT;
pc_bus   : INPUT;
RD       : INPUT;
scan_clk : INPUT;
sw_bus   : INPUT;
WE       : INPUT;
161clr   : INPUT;
161load  : INPUT;
161pc    : INPUT;

-- Node name is 'adr0' 
-- Equation name is 'adr0', type is output 
adr0     =  _LC5_B8;

-- Node name is 'adr1' 
-- Equation name is 'adr1', type is output 
adr1     =  _LC6_B8;

-- Node name is 'adr2' 
-- Equation name is 'adr2', type is output 
adr2     =  _LC7_B8;

-- Node name is 'adr3' 
-- Equation name is 'adr3', type is output 
adr3     =  _LC4_B8;

-- Node name is 'adr4' 
-- Equation name is 'adr4', type is output 
adr4     =  _LC2_B8;

-- Node name is 'adr5' 
-- Equation name is 'adr5', type is output 
adr5     =  _LC5_B5;

-- Node name is 'adr6' 
-- Equation name is 'adr6', type is output 
adr6     =  _LC8_B8;

-- Node name is 'adr7' 
-- Equation name is 'adr7', type is output 
adr7     =  _LC1_B8;

-- Node name is 'd0' 
-- Equation name is 'd0', type is bidir 
d0       = TRI(_LC3_B16,  _LC1_B18);

-- Node name is 'd1' 
-- Equation name is 'd1', type is bidir 
d1       = TRI(_LC8_B20,  _LC1_B18);

-- Node name is 'd2' 
-- Equation name is 'd2', type is bidir 
d2       = TRI(_LC2_B18,  _LC1_B18);

-- Node name is 'd3' 
-- Equation name is 'd3', type is bidir 
d3       = TRI(_LC2_B16,  _LC1_B18);

-- Node name is 'd4' 
-- Equation name is 'd4', type is bidir 
d4       = TRI(_LC4_B16,  _LC1_B18);

-- Node name is 'd5' 
-- Equation name is 'd5', type is bidir 
d5       = TRI(_LC1_B16,  _LC1_B18);

-- Node name is 'd6' 
-- Equation name is 'd6', type is bidir 
d6       = TRI(_LC3_B18,  _LC1_B18);

-- Node name is 'd7' 
-- Equation name is 'd7', type is bidir 
d7       = TRI(_LC4_B18,  _LC1_B18);

-- Node name is 'GW' 
-- Equation name is 'GW', type is output 
GW       = !_LC3_E17;

-- Node name is 'GW~1' 
-- Equation name is 'GW~1', location is LC3_E17, type is buried.
-- synthesized logic cell 
_LC3_E17 = LCELL( scan_clk);

-- Node name is 'seg_a' 
-- Equation name is 'seg_a', type is output 
seg_a    =  _LC6_E13;

-- Node name is 'seg_b' 
-- Equation name is 'seg_b', type is output 
seg_b    =  _LC2_E14;

-- Node name is 'seg_c' 
-- Equation name is 'seg_c', type is output 
seg_c    =  _LC6_E16;

-- Node name is 'seg_d' 
-- Equation name is 'seg_d', type is output 
seg_d    =  _LC8_E16;

-- Node name is 'seg_e' 
-- Equation name is 'seg_e', type is output 
seg_e    =  _LC6_E17;

-- Node name is 'seg-f' 
-- Equation name is 'seg-f', type is output 
seg-f    =  _LC2_E17;

-- Node name is 'seg_g' 
-- Equation name is 'seg_g', type is output 
seg_g    =  _LC5_E17;

-- Node name is 'SW' 
-- Equation name is 'SW', type is output 
SW       =  _LC8_E17;

-- Node name is 'SW~1' 
-- Equation name is 'SW~1', location is LC8_E17, type is buried.
-- synthesized logic cell 
_LC8_E17 = LCELL( scan_clk);

-- Node name is '|BCD_7SEG:61|:456' 
-- Equation name is '_LC1_E16', type is buried 
!_LC1_E16 = _LC1_E16~NOT;
_LC1_E16~NOT = LCELL( _EQ001);
  _EQ001 = !_LC1_E17
         #  _LC8_B19
         # !_LC2_B20
         # !_LC4_E17;

-- Node name is '|BCD_7SEG:61|:492' 
-- Equation name is '_LC3_E14', type is buried 
_LC3_E14 = LCELL( _EQ002);
  _EQ002 =  _LC1_E17 & !_LC2_B20 & !_LC4_E17 & !_LC8_B19;

-- Node name is '|BCD_7SEG:61|:528' 
-- Equation name is '_LC2_E16', type is buried 
!_LC2_E16 = _LC2_E16~NOT;
_LC2_E16~NOT = LCELL( _EQ003);
  _EQ003 =  _LC1_E17
         #  _LC8_B19
         #  _LC2_B20
         # !_LC4_E17;

-- Node name is '|BCD_7SEG:61|:540' 
-- Equation name is '_LC3_E16', type is buried 
_LC3_E16 = LCELL( _EQ004);
  _EQ004 = !_LC1_E17 & !_LC2_B20 & !_LC4_E17 & !_LC8_B19;

-- Node name is '|BCD_7SEG:61|:545' 
-- Equation name is '_LC5_E17', type is buried 
_LC5_E17 = LCELL( _EQ005);
  _EQ005 = !_LC1_E16 & !_LC2_E16 & !_LC3_E16;

-- Node name is '|BCD_7SEG:61|~579~1' 
-- Equation name is '_LC6_E14', type is buried 
-- synthesized logic cell 
!_LC6_E14 = _LC6_E14~NOT;
_LC6_E14~NOT = LCELL( _EQ006);
  _EQ006 = !_LC1_E17
         #  _LC8_B19
         #  _LC2_B20 &  _LC4_E17
         # !_LC2_B20 & !_LC4_E17;

-- Node name is '|BCD_7SEG:61|:591' 
-- Equation name is '_LC2_E17', type is buried 
_LC2_E17 = LCELL( _EQ007);
  _EQ007 =  _LC2_B20 &  _LC8_B19
         #  _LC1_E17 &  _LC2_B20 & !_LC4_E17
         #  _LC1_E17 & !_LC2_B20 & !_LC8_B19
         #  _LC1_E17 & !_LC4_E17 & !_LC8_B19
         # !_LC1_E17 &  _LC8_B19
         # !_LC1_E17 & !_LC2_B20 & !_LC4_E17
         # !_LC2_B20 & !_LC4_E17 & !_LC8_B19;

-- Node name is '|BCD_7SEG:61|:633' 
-- Equation name is '_LC7_E17', type is buried 
_LC7_E17 = LCELL( _EQ008);
  _EQ008 =  _LC2_B20 &  _LC8_B19
         #  _LC1_E17 &  _LC8_B19
         #  _LC2_B20 & !_LC4_E17
         # !_LC1_E17 & !_LC4_E17
         # !_LC4_E17 &  _LC8_B19
         # !_LC1_E17 & !_LC2_B20 & !_LC8_B19;

-- Node name is '|BCD_7SEG:61|:639' 
-- Equation name is '_LC6_E17', type is buried 
_LC6_E17 = LCELL( _EQ009);
  _EQ009 = !_LC2_E16 &  _LC7_E17
         #  _LC3_E16;

-- Node name is '|BCD_7SEG:61|:663' 
-- Equation name is '_LC8_E14', type is buried 
_LC8_E14 = LCELL( _EQ010);
  _EQ010 =  _LC1_E17 & !_LC4_E17 &  _LC8_B19
         #  _LC1_E17 & !_LC2_B20 &  _LC8_B19
         # !_LC2_B20 & !_LC4_E17 &  _LC8_B19
         # !_LC1_E17 &  _LC2_B20 &  _LC4_E17 &  _LC8_B19;

-- Node name is '|BCD_7SEG:61|:680' 
-- Equation name is '_LC1_E14', type is buried 
_LC1_E14 = LCELL( _EQ011);
  _EQ011 = !_LC1_E16 & !_LC3_E14 &  _LC8_E14
         # !_LC3_E14 &  _LC6_E14;

-- Node name is '|BCD_7SEG:61|:687' 
-- Equation name is '_LC8_E16', type is buried 
_LC8_E16 = LCELL( _EQ012);
  _EQ012 =  _LC1_E14 & !_LC2_E16
         # !_LC2_E16 &  _LC5_E16
         #  _LC3_E16;

-- Node name is '|BCD_7SEG:61|:734' 
-- Equation name is '_LC7_E16', type is buried 
_LC7_E16 = LCELL( _EQ013);
  _EQ013 =  _LC1_E17 & !_LC2_B20 &  _LC4_E17
         # !_LC1_E17 &  _LC2_B20 &  _LC4_E17
         #  _LC1_E17 & !_LC4_E17 & !_LC8_B19
         #  _LC1_E17 & !_LC2_B20 & !_LC8_B19
         #  _LC2_B20 &  _LC4_E17 & !_LC8_B19
         # !_LC2_B20 &  _LC4_E17 &  _LC8_B19
         # !_LC1_E17 &  _LC8_B19;

-- Node name is '|BCD_7SEG:61|:735' 
-- Equation name is '_LC6_E16', type is buried 
_LC6_E16 = LCELL( _EQ014);
  _EQ014 =  _LC3_E16
         #  _LC2_E16
         #  _LC7_E16;

-- Node name is '|BCD_7SEG:61|:755' 
-- Equation name is '_LC5_E14', type is buried 
_LC5_E14 = LCELL( _EQ015);