📄 test_ram.rpt
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Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 38/96 ( 39%)
Total logic cells used: 81/1152 ( 7%)
Total embedded cells used: 8/48 ( 16%)
Total EABs used: 1/6 ( 16%)
Average fan-in: 3.29/4 ( 82%)
Total fan-in: 267/4608 ( 5%)
Total input pins required: 14
Total input I/O cell registers required: 0
Total output pins required: 17
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 8
Total reserved pins required 0
Total logic cells required: 81
Total flipflops required: 24
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 14/1152 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 1 0 0 8 0 0 0 0 8 0 0 0 7 0 8 8 8 0 0 7 8 55/8
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 0 8 8 0 0 0 0 0 0 0 25/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 1 0 0 8 0 0 0 0 8 1 8 0 15 8 8 8 8 0 0 7 9 81/8
Device-Specific Information: e:\xyq\maxplus\sy4\test_ram.rpt
test_ram
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
122 - - - 13 INPUT 0 0 0 17 clk_cdu
95 - - B -- INPUT 0 0 0 8 clr_cdu
128 - - - 13 INPUT 0 0 0 1 cp161ldar
9 - - B -- BIDIR 0 1 0 3 d0
10 - - B -- BIDIR 0 1 0 3 d1
12 - - C -- BIDIR 0 1 0 3 d2
13 - - C -- BIDIR 0 1 0 3 d3
17 - - D -- BIDIR 0 1 0 3 d4
18 - - D -- BIDIR 0 1 0 3 d5
19 - - D -- BIDIR 0 1 0 3 d6
20 - - D -- BIDIR 0 1 0 3 d7
92 - - C -- INPUT 0 0 0 4 en_cdu
72 - - - 03 INPUT 0 0 0 1 LDAR
79 - - F -- INPUT 0 0 0 10 MEMENAB
82 - - E -- INPUT 0 0 0 9 pc_bus
78 - - F -- INPUT 0 0 0 10 RD
125 - - - -- INPUT 0 0 0 6 scan_clk
83 - - E -- INPUT 0 0 0 9 sw_bus
73 - - - 01 INPUT 0 0 0 1 WE
86 - - E -- INPUT 0 0 0 8 161clr
87 - - E -- INPUT 0 0 0 8 161load
88 - - D -- INPUT 0 0 0 1 161pc
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\xyq\maxplus\sy4\test_ram.rpt
test_ram
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - D -- OUTPUT 0 1 0 0 adr0
22 - - D -- OUTPUT 0 1 0 0 adr1
23 - - D -- OUTPUT 0 1 0 0 adr2
26 - - E -- OUTPUT 0 1 0 0 adr3
27 - - E -- OUTPUT 0 1 0 0 adr4
28 - - E -- OUTPUT 0 1 0 0 adr5
29 - - E -- OUTPUT 0 1 0 0 adr6
30 - - F -- OUTPUT 0 1 0 0 adr7
9 - - B -- TRI 0 1 0 3 d0
10 - - B -- TRI 0 1 0 3 d1
12 - - C -- TRI 0 1 0 3 d2
13 - - C -- TRI 0 1 0 3 d3
17 - - D -- TRI 0 1 0 3 d4
18 - - D -- TRI 0 1 0 3 d5
19 - - D -- TRI 0 1 0 3 d6
20 - - D -- TRI 0 1 0 3 d7
102 - - A -- OUTPUT 0 1 0 0 GW
51 - - - 14 OUTPUT 0 1 0 0 seg_a
49 - - - 14 OUTPUT 0 1 0 0 seg_b
48 - - - 15 OUTPUT 0 1 0 0 seg_c
47 - - - 16 OUTPUT 0 1 0 0 seg_d
46 - - - 17 OUTPUT 0 1 0 0 seg_e
44 - - - 18 OUTPUT 0 1 0 0 seg-f
43 - - - 18 OUTPUT 0 1 0 0 seg_g
8 - - A -- OUTPUT 0 1 0 0 SW
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\xyq\maxplus\sy4\test_ram.rpt
test_ram
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - E 16 OR2 ! 0 4 0 2 |BCD_7SEG:61|:456
- 3 - E 14 AND2 0 4 0 2 |BCD_7SEG:61|:492
- 2 - E 16 OR2 ! 0 4 0 6 |BCD_7SEG:61|:528
- 3 - E 16 AND2 0 4 0 6 |BCD_7SEG:61|:540
- 5 - E 17 AND2 0 3 1 0 |BCD_7SEG:61|:545
- 6 - E 14 OR2 s ! 0 4 0 2 |BCD_7SEG:61|~579~1
- 2 - E 17 OR2 0 4 1 0 |BCD_7SEG:61|:591
- 7 - E 17 OR2 0 4 0 1 |BCD_7SEG:61|:633
- 6 - E 17 OR2 0 3 1 0 |BCD_7SEG:61|:639
- 8 - E 14 OR2 0 4 0 1 |BCD_7SEG:61|:663
- 1 - E 14 OR2 0 4 0 1 |BCD_7SEG:61|:680
- 8 - E 16 OR2 0 4 1 0 |BCD_7SEG:61|:687
- 7 - E 16 OR2 0 4 0 1 |BCD_7SEG:61|:734
- 6 - E 16 OR2 0 3 1 0 |BCD_7SEG:61|:735
- 5 - E 14 OR2 0 4 0 1 |BCD_7SEG:61|:755
- 4 - E 14 OR2 s 0 4 0 1 |BCD_7SEG:61|~783~1
- 2 - E 14 OR2 0 4 1 0 |BCD_7SEG:61|:783
- 7 - E 14 OR2 s 0 4 0 1 |BCD_7SEG:61|~816~1
- 4 - E 16 OR2 0 4 0 1 |BCD_7SEG:61|:824
- 5 - E 16 AND2 s 0 3 0 3 |BCD_7SEG:61|~825~1
- 6 - E 13 OR2 0 4 1 0 |BCD_7SEG:61|:831
- 6 - B 20 DFFE 3 0 0 5 |cdu16:74|74163:8|f74163:sub|QA (|cdu16:74|74163:8|f74163:sub|:34)
- 3 - B 20 AND2 0 2 0 1 |cdu16:74|74163:8|f74163:sub|:106
- 5 - B 20 DFFE 3 1 0 4 |cdu16:74|74163:8|f74163:sub|QB (|cdu16:74|74163:8|f74163:sub|:111)
- 7 - B 20 DFFE 3 1 0 3 |cdu16:74|74163:8|f74163:sub|QC (|cdu16:74|74163:8|f74163:sub|:122)
- 4 - B 20 AND2 1 3 0 4 |cdu16:74|74163:8|f74163:sub|:130
- 2 - B 19 DFFE 2 1 0 5 |cdu16:74|74163:8|f74163:sub|QD (|cdu16:74|74163:8|f74163:sub|:134)
- 6 - B 19 DFFE 2 2 0 4 |cdu16:75|74163:8|f74163:sub|QA (|cdu16:75|74163:8|f74163:sub|:34)
- 4 - B 19 DFFE 2 2 0 3 |cdu16:75|74163:8|f74163:sub|QB (|cdu16:75|74163:8|f74163:sub|:111)
- 5 - B 19 AND2 0 4 0 2 |cdu16:75|74163:8|f74163:sub|:119
- 3 - B 19 DFFE 2 1 0 3 |cdu16:75|74163:8|f74163:sub|QC (|cdu16:75|74163:8|f74163:sub|:122)
- 1 - B 19 DFFE 2 2 0 2 |cdu16:75|74163:8|f74163:sub|QD (|cdu16:75|74163:8|f74163:sub|:134)
- 3 - E 17 LCELL s 1 0 1 0 GW~1
- - 4 B -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_0
- - 8 B -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_1
- - 6 B -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_2
- - 5 B -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_3
- - 2 B -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_4
- - 1 B -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_5
- - 3 B -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_6
- - 7 B -- MEM_SGMT 1 10 0 1 |LPM_RAM_IO:57|altram:sram|segment0_7
- 7 - B 18 OR2 s 2 2 0 1 |LPM_RAM_IO:57|datatri0~1~3~2
- 3 - B 16 OR2 2 2 1 0 |LPM_RAM_IO:57|datatri0~1~3
- 1 - B 20 OR2 s 2 2 0 1 |LPM_RAM_IO:57|datatri1~1~3~2
- 8 - B 20 OR2 2 2 1 0 |LPM_RAM_IO:57|datatri1~1~3
- 5 - B 18 OR2 s 2 2 0 1 |LPM_RAM_IO:57|datatri2~1~3~2
- 2 - B 18 OR2 2 2 1 0 |LPM_RAM_IO:57|datatri2~1~3
- 5 - B 16 OR2 s 2 2 0 1 |LPM_RAM_IO:57|datatri3~1~3~2
- 2 - B 16 OR2 2 2 1 0 |LPM_RAM_IO:57|datatri3~1~3
- 6 - B 16 OR2 s 2 2 0 1 |LPM_RAM_IO:57|datatri4~1~3~2
- 4 - B 16 OR2 2 2 1 0 |LPM_RAM_IO:57|datatri4~1~3
- 3 - B 24 OR2 s 2 2 0 1 |LPM_RAM_IO:57|datatri5~1~3~2
- 1 - B 16 OR2 2 2 1 0 |LPM_RAM_IO:57|datatri5~1~3
- 6 - B 18 OR2 s 2 2 0 1 |LPM_RAM_IO:57|datatri6~1~3~2
- 3 - B 18 OR2 2 2 1 0 |LPM_RAM_IO:57|datatri6~1~3
- 1 - B 18 OR2 4 0 0 0 |LPM_RAM_IO:57|datatri7~1~2
- 8 - B 18 OR2 s 2 2 0 1 |LPM_RAM_IO:57|datatri7~1~3~2
- 4 - B 18 OR2 2 2 1 0 |LPM_RAM_IO:57|datatri7~1~3
- 7 - B 16 AND2 3 0 0 8 |LPM_RAM_IO:57|:91
- 4 - E 17 OR2 ! 1 2 0 12 |saomiao:62|74157:9|Y1 (|saomiao:62|74157:9|:22)
- 2 - B 20 OR2 1 2 0 13 |saomiao:62|74157:9|Y2 (|saomiao:62|74157:9|:23)
- 1 - E 17 OR2 ! 1 2 0 13 |saomiao:62|74157:9|Y3 (|saomiao:62|74157:9|:24)
- 8 - B 19 OR2 1 2 0 13 |saomiao:62|74157:9|Y4 (|saomiao:62|74157:9|:25)
- 8 - E 17 LCELL s 1 0 1 0 SW~1
- 7 - B 19 AND2 0 2 0 1 :60
- 3 - B 08 AND2 2 0 0 8 :80
- 6 - D 24 AND2 2 0 0 8 :81
- 3 - B 23 DFFE 2 2 0 5 |74161:116|f74161:sub|QA (|74161:116|f74161:sub|:9)
- 4 - B 23 AND2 0 2 0 1 |74161:116|f74161:sub|:84
- 2 - B 23 DFFE 2 3 0 4 |74161:116|f74161:sub|QB (|74161:116|f74161:sub|:87)
- 6 - B 23 AND2 0 3 0 1 |74161:116|f74161:sub|:94
- 1 - B 23 DFFE 2 3 0 3 |74161:116|f74161:sub|QC (|74161:116|f74161:sub|:99)
- 8 - B 23 AND2 0 4 0 4 |74161:116|f74161:sub|:104
- 5 - B 23 DFFE 2 3 0 2 |74161:116|f74161:sub|QD (|74161:116|f74161:sub|:110)
- 4 - B 24 DFFE 2 3 0 4 |74161:117|f74161:sub|QA (|74161:117|f74161:sub|:9)
- 5 - B 24 AND2 0 2 0 1 |74161:117|f74161:sub|:80
- 7 - B 24 AND2 0 3 0 1 |74161:117|f74161:sub|:84
- 6 - B 24 DFFE 2 3 0 3 |74161:117|f74161:sub|QB (|74161:117|f74161:sub|:87)
- 8 - B 24 AND2 0 4 0 1 |74161:117|f74161:sub|:94
- 2 - B 24 DFFE 2 3 0 2 |74161:117|f74161:sub|QC (|74161:117|f74161:sub|:99)
- 1 - B 24 DFFE 2 3 0 1 |74161:117|f74161:sub|QD (|74161:117|f74161:sub|:110)
- 1 - B 08 DFFE 0 2 1 8 |74273:115|Q8 (|74273:115|:12)
- 8 - B 08 DFFE 0 2 1 8 |74273:115|Q7 (|74273:115|:13)
- 5 - B 05 DFFE 0 2 1 8 |74273:115|Q6 (|74273:115|:14)
- 2 - B 08 DFFE 0 2 1 8 |74273:115|Q5 (|74273:115|:15)
- 4 - B 08 DFFE 0 2 1 8 |74273:115|Q4 (|74273:115|:16)
- 7 - B 08 DFFE 0 2 1 8 |74273:115|Q3 (|74273:115|:17)
- 6 - B 08 DFFE 0 2 1 8 |74273:115|Q2 (|74273:115|:18)
- 5 - B 08 DFFE 0 2 1 8 |74273:115|Q1 (|74273:115|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\xyq\maxplus\sy4\test_ram.rpt
test_ram
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 30/ 96( 31%) 12/ 48( 25%) 24/ 48( 50%) 1/16( 6%) 0/16( 0%) 2/16( 12%)
C: 3/ 96( 3%) 0/ 48( 0%) 2/ 48( 4%) 1/16( 6%) 0/16( 0%) 2/16( 12%)
D: 8/ 96( 8%) 0/ 48( 0%) 5/ 48( 10%) 1/16( 6%) 3/16( 18%) 4/16( 25%)
E: 9/ 96( 9%) 0/ 48( 0%) 13/ 48( 27%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
F: 3/ 96( 3%) 0/ 48( 0%) 0/ 48( 0%) 2/16( 12%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
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