📄 cdu.rpt
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Device-Specific Information: e:\xyq\maxplus\jibenzujian\cdu.rpt
cdu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 01 DFFE + 2 0 1 4 |74163:8|f74163:sub|QA (|74163:8|f74163:sub|:34)
- 4 - A 01 AND2 0 2 0 1 |74163:8|f74163:sub|:106
- 1 - A 01 DFFE + 2 1 1 3 |74163:8|f74163:sub|QB (|74163:8|f74163:sub|:111)
- 6 - A 01 AND2 0 3 0 1 |74163:8|f74163:sub|:117
- 5 - A 01 DFFE + 2 1 1 2 |74163:8|f74163:sub|QC (|74163:8|f74163:sub|:122)
- 7 - A 01 AND2 0 4 1 0 |74163:8|f74163:sub|:128
- 2 - A 01 DFFE + 2 1 1 1 |74163:8|f74163:sub|QD (|74163:8|f74163:sub|:134)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\xyq\maxplus\jibenzujian\cdu.rpt
cdu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\xyq\maxplus\jibenzujian\cdu.rpt
cdu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: e:\xyq\maxplus\jibenzujian\cdu.rpt
cdu
** EQUATIONS **
clk : INPUT;
clr_181 : INPUT;
en_181 : INPUT;
-- Node name is 'cy'
-- Equation name is 'cy', type is output
cy = _LC7_A1;
-- Node name is 's0'
-- Equation name is 's0', type is output
s0 = _LC3_A1;
-- Node name is 's1'
-- Equation name is 's1', type is output
s1 = _LC1_A1;
-- Node name is 's2'
-- Equation name is 's2', type is output
s2 = _LC5_A1;
-- Node name is 's3'
-- Equation name is 's3', type is output
s3 = _LC2_A1;
-- Node name is '|74163:8|f74163:sub|:34' = '|74163:8|f74163:sub|QA'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = clr_181 & !en_181 & _LC3_A1
# clr_181 & en_181 & !_LC3_A1;
-- Node name is '|74163:8|f74163:sub|:111' = '|74163:8|f74163:sub|QB'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = clr_181 & _LC1_A1 & !_LC3_A1
# clr_181 & !en_181 & _LC1_A1
# clr_181 & en_181 & !_LC1_A1 & _LC3_A1;
-- Node name is '|74163:8|f74163:sub|:122' = '|74163:8|f74163:sub|QC'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = clr_181 & !_LC4_A1 & _LC5_A1
# clr_181 & !en_181 & _LC5_A1
# clr_181 & en_181 & _LC4_A1 & !_LC5_A1;
-- Node name is '|74163:8|f74163:sub|:134' = '|74163:8|f74163:sub|QD'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = clr_181 & _LC2_A1 & !_LC6_A1
# clr_181 & !en_181 & _LC2_A1
# clr_181 & en_181 & !_LC2_A1 & _LC6_A1;
-- Node name is '|74163:8|f74163:sub|:106'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = LCELL( _EQ005);
_EQ005 = _LC1_A1 & _LC3_A1;
-- Node name is '|74163:8|f74163:sub|:117'
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = LCELL( _EQ006);
_EQ006 = _LC1_A1 & _LC3_A1 & _LC5_A1;
-- Node name is '|74163:8|f74163:sub|:128'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ007);
_EQ007 = _LC1_A1 & _LC2_A1 & _LC3_A1 & _LC5_A1;
Project Information e:\xyq\maxplus\jibenzujian\cdu.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,697K
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