📄 scan.rpt
字号:
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\shiyan3\scan.rpt
scan
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 2 scan_clk
Device-Specific Information: d:\shiyan3\scan.rpt
scan
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 2 CLR
Device-Specific Information: d:\shiyan3\scan.rpt
scan
** EQUATIONS **
CLR : INPUT;
in0 : INPUT;
in1 : INPUT;
in2 : INPUT;
in3 : INPUT;
in4 : INPUT;
in5 : INPUT;
in6 : INPUT;
in7 : INPUT;
scan_clk : INPUT;
-- Node name is 'Q0'
-- Equation name is 'Q0', type is output
Q0 = _LC4_A22;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = _LC8_A22;
-- Node name is 'seg_a'
-- Equation name is 'seg_a', type is output
seg_a = _LC2_A20;
-- Node name is 'seg_b'
-- Equation name is 'seg_b', type is output
seg_b = _LC3_A23;
-- Node name is 'seg_c'
-- Equation name is 'seg_c', type is output
seg_c = _LC1_A23;
-- Node name is 'seg_d'
-- Equation name is 'seg_d', type is output
seg_d = _LC8_A20;
-- Node name is 'seg_e'
-- Equation name is 'seg_e', type is output
seg_e = _LC2_A23;
-- Node name is 'seg_f'
-- Equation name is 'seg_f', type is output
seg_f = _LC1_A22;
-- Node name is 'seg_g'
-- Equation name is 'seg_g', type is output
seg_g = _LC7_A22;
-- Node name is ':34'
-- Equation name is '_LC4_A22', type is buried
_LC4_A22 = DFFE(!_LC4_A22, GLOBAL( scan_clk), GLOBAL( CLR), VCC, VCC);
-- Node name is ':42'
-- Equation name is '_LC8_A22', type is buried
_LC8_A22 = DFFE( _EQ001, GLOBAL( scan_clk), GLOBAL( CLR), VCC, VCC);
_EQ001 = _LC4_A22 & !_LC8_A22;
-- Node name is ':64'
-- Equation name is '_LC6_A22', type is buried
_LC6_A22 = LCELL( _EQ002);
_EQ002 = in3 & _LC4_A22 & !_LC8_A22
# in7 & !_LC4_A22 & _LC8_A22;
-- Node name is ':65'
-- Equation name is '_LC2_A22', type is buried
_LC2_A22 = LCELL( _EQ003);
_EQ003 = in2 & _LC4_A22 & !_LC8_A22
# in6 & !_LC4_A22 & _LC8_A22;
-- Node name is ':66'
-- Equation name is '_LC5_A22', type is buried
!_LC5_A22 = _LC5_A22~NOT;
_LC5_A22~NOT = LCELL( _EQ004);
_EQ004 = !_LC4_A22 & !_LC8_A22
# !in1 & !_LC8_A22
# _LC4_A22 & _LC8_A22
# !in1 & _LC4_A22
# !in5 & _LC8_A22
# !in5 & !_LC4_A22
# !in1 & !in5;
-- Node name is ':67'
-- Equation name is '_LC3_A22', type is buried
_LC3_A22 = LCELL( _EQ005);
_EQ005 = in0 & _LC4_A22 & !_LC8_A22
# in4 & !_LC4_A22 & _LC8_A22;
-- Node name is ':68'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = LCELL( _EQ006);
_EQ006 = !_LC2_A22 & !_LC3_A22 & !_LC5_A22 & !_LC6_A22;
-- Node name is ':248'
-- Equation name is '_LC6_A20', type is buried
_LC6_A20 = LCELL( _EQ007);
_EQ007 = _LC2_A22 & _LC3_A22 & _LC5_A22 & _LC6_A22;
-- Node name is '~283~1'
-- Equation name is '~283~1', location is LC4_A20, type is buried.
-- synthesized logic cell
_LC4_A20 = LCELL( _EQ008);
_EQ008 = _LC2_A22 & _LC3_A22 & !_LC6_A22
# !_LC2_A22 & !_LC3_A22 & !_LC6_A22
# _LC2_A22 & !_LC3_A22 & _LC6_A22
# _LC5_A22 & !_LC6_A22;
-- Node name is ':283'
-- Equation name is '_LC2_A20', type is buried
_LC2_A20 = LCELL( _EQ009);
_EQ009 = _LC4_A20
# _LC5_A20
# _LC6_A20;
-- Node name is '~286~1'
-- Equation name is '~286~1', location is LC5_A23, type is buried.
-- synthesized logic cell
_LC5_A23 = LCELL( _EQ010);
_EQ010 = _LC2_A22 & _LC3_A22 & _LC5_A22 & !_LC6_A22
# !_LC2_A22 & _LC3_A22 & !_LC5_A22 & !_LC6_A22;
-- Node name is '~286~2'
-- Equation name is '~286~2', location is LC5_A20, type is buried.
-- synthesized logic cell
_LC5_A20 = LCELL( _EQ011);
_EQ011 = !_LC2_A22 & !_LC3_A22 & _LC6_A22
# !_LC2_A22 & !_LC5_A22 & _LC6_A22;
-- Node name is ':286'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = LCELL( _EQ012);
_EQ012 = _LC3_A22 & _LC5_A22 & !_LC6_A22
# !_LC2_A22 & !_LC6_A22
# _LC3_A22 & !_LC5_A22 & _LC6_A22
# !_LC2_A22 & !_LC3_A22
# !_LC2_A22 & !_LC5_A22
# !_LC3_A22 & !_LC5_A22 & !_LC6_A22;
-- Node name is '~289~1'
-- Equation name is '~289~1', location is LC7_A23, type is buried.
-- synthesized logic cell
_LC7_A23 = LCELL( _EQ013);
_EQ013 = !_LC2_A22 & _LC6_A22
# _LC2_A22 & !_LC5_A22 & !_LC6_A22
# _LC2_A22 & !_LC3_A22 & !_LC6_A22;
-- Node name is ':289'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = LCELL( _EQ014);
_EQ014 = _LC4_A23
# _LC5_A23
# _LC6_A23
# _LC7_A23;
-- Node name is '~292~1'
-- Equation name is '~292~1', location is LC1_A20, type is buried.
-- synthesized logic cell
_LC1_A20 = LCELL( _EQ015);
_EQ015 = _LC2_A22 & _LC3_A22 & !_LC5_A22 & !_LC6_A22
# !_LC2_A22 & _LC3_A22 & _LC5_A22 & !_LC6_A22
# !_LC2_A22 & !_LC3_A22 & !_LC5_A22 & _LC6_A22;
-- Node name is '~292~2'
-- Equation name is '~292~2', location is LC3_A20, type is buried.
-- synthesized logic cell
_LC3_A20 = LCELL( _EQ016);
_EQ016 = !_LC2_A22 & _LC3_A22 & _LC5_A22 & _LC6_A22
# !_LC2_A22 & !_LC3_A22 & !_LC6_A22
# _LC2_A22 & !_LC3_A22 & _LC6_A22
# !_LC3_A22 & _LC5_A22 & !_LC6_A22
# _LC2_A22 & !_LC5_A22 & _LC6_A22;
-- Node name is ':292'
-- Equation name is '_LC8_A20', type is buried
_LC8_A20 = LCELL( _EQ017);
_EQ017 = _LC1_A20
# _LC3_A20;
-- Node name is ':295'
-- Equation name is '_LC2_A23', type is buried
_LC2_A23 = LCELL( _EQ018);
_EQ018 = _LC3_A22 & _LC5_A22 & _LC6_A22
# !_LC2_A22 & !_LC3_A22
# !_LC3_A22 & !_LC5_A22 & _LC6_A22
# _LC2_A22 & _LC5_A22 & _LC6_A22
# !_LC3_A22 & _LC5_A22 & !_LC6_A22
# _LC2_A22 & _LC3_A22 & _LC6_A22;
-- Node name is ':298'
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = LCELL( _EQ019);
_EQ019 = _LC5_A22 & _LC6_A22
# !_LC3_A22 & _LC6_A22
# !_LC2_A22 & _LC6_A22
# !_LC3_A22 & !_LC5_A22
# _LC2_A22 & !_LC5_A22 & !_LC6_A22
# _LC2_A22 & !_LC3_A22;
-- Node name is '~301~1'
-- Equation name is '~301~1', location is LC6_A23, type is buried.
-- synthesized logic cell
_LC6_A23 = LCELL( _EQ020);
_EQ020 = !_LC2_A22 & _LC3_A22 & _LC5_A22 & !_LC6_A22
# _LC2_A22 & _LC3_A22 & !_LC5_A22 & _LC6_A22;
-- Node name is ':301'
-- Equation name is '_LC7_A22', type is buried
_LC7_A22 = LCELL( _EQ021);
_EQ021 = _LC5_A22 & _LC6_A22
# !_LC2_A22 & _LC6_A22
# _LC2_A22 & !_LC5_A22 & !_LC6_A22
# !_LC3_A22 & _LC5_A22
# !_LC2_A22 & _LC5_A22
# _LC3_A22 & _LC6_A22;
Project Information d:\shiyan3\scan.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,128K
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