📄 databusjiben.rpt
字号:
- 5 - B 22 DFFE 0 2 1 8 |shiyan3jiben:1|74273:5|Q1 (|shiyan3jiben:1|74273:5|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\xyq\maxplus\sy4\databusjiben.rpt
databusjiben
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 62/ 96( 64%) 34/ 48( 70%) 15/ 48( 31%) 0/16( 0%) 0/16( 0%) 7/16( 43%)
C: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
E: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
F: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
10: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 1/4( 25%) 0/4( 0%) 1/4( 25%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
22: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\xyq\maxplus\sy4\databusjiben.rpt
databusjiben
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 8 |fuheys:29|:6
LCELL 8 |fuheys:29|:7
LCELL 8 |fuheys:29|:8
LCELL 8 |fuheys:29|:9
LCELL 8 |shiyan3jiben:1|:27
LCELL 8 |shiyan3jiben:1|:32
Device-Specific Information: e:\xyq\maxplus\sy4\databusjiben.rpt
databusjiben
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 161clr
Device-Specific Information: e:\xyq\maxplus\sy4\databusjiben.rpt
databusjiben
** EQUATIONS **
ALU_BUS : INPUT;
clk_cdu : INPUT;
CN : INPUT;
cpldar : INPUT;
CP_T : INPUT;
enable : INPUT;
inputd0 : INPUT;
inputd1 : INPUT;
inputd2 : INPUT;
inputd3 : INPUT;
inputd4 : INPUT;
inputd5 : INPUT;
inputd6 : INPUT;
inputd7 : INPUT;
LDAR : INPUT;
LDDR1 : INPUT;
LDDR2 : INPUT;
LDR4 : INPUT;
LDR5 : INPUT;
M : INPUT;
pc_bus : INPUT;
RD : INPUT;
R4_BUS : INPUT;
R5_BUS : INPUT;
sw_bus : INPUT;
s0 : INPUT;
s1 : INPUT;
s2 : INPUT;
s3 : INPUT;
WE : INPUT;
161clr : INPUT;
161load : INPUT;
161pc : INPUT;
-- Node name is 'adr0'
-- Equation name is 'adr0', type is output
adr0 = _LC5_B22;
-- Node name is 'adr1'
-- Equation name is 'adr1', type is output
adr1 = _LC2_B22;
-- Node name is 'adr2'
-- Equation name is 'adr2', type is output
adr2 = _LC4_B22;
-- Node name is 'adr3'
-- Equation name is 'adr3', type is output
adr3 = _LC3_B22;
-- Node name is 'adr4'
-- Equation name is 'adr4', type is output
adr4 = _LC8_B22;
-- Node name is 'adr5'
-- Equation name is 'adr5', type is output
adr5 = _LC7_B22;
-- Node name is 'adr6'
-- Equation name is 'adr6', type is output
adr6 = _LC3_B18;
-- Node name is 'adr7'
-- Equation name is 'adr7', type is output
adr7 = _LC6_B22;
-- Node name is 'cn4'
-- Equation name is 'cn4', type is output
cn4 = _LC5_B9;
-- Node name is 'dout0'
-- Equation name is 'dout0', type is bidir
dout0 = TRI(_LC4_B15, _LC4_B10);
-- Node name is 'dout1'
-- Equation name is 'dout1', type is bidir
dout1 = TRI(_LC5_B21, _LC4_B10);
-- Node name is 'dout2'
-- Equation name is 'dout2', type is bidir
dout2 = TRI(_LC1_B10, _LC4_B10);
-- Node name is 'dout3'
-- Equation name is 'dout3', type is bidir
dout3 = TRI(_LC1_B14, _LC4_B10);
-- Node name is 'dout4'
-- Equation name is 'dout4', type is bidir
dout4 = TRI(_LC6_B7, _LC4_B10);
-- Node name is 'dout5'
-- Equation name is 'dout5', type is bidir
dout5 = TRI(_LC1_B3, _LC4_B10);
-- Node name is 'dout6'
-- Equation name is 'dout6', type is bidir
dout6 = TRI(_LC4_B4, _LC4_B10);
-- Node name is 'dout7'
-- Equation name is 'dout7', type is bidir
dout7 = TRI(_LC7_B10, _LC4_B10);
-- Node name is '|fuheys:29|:6'
-- Equation name is '_LC3_B6', type is buried
_LC3_B6 = LCELL( _EQ001);
_EQ001 = !CP_T & LDDR1;
-- Node name is '|fuheys:29|:7'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = LCELL( _EQ002);
_EQ002 = !CP_T & LDDR2;
-- Node name is '|fuheys:29|:8'
-- Equation name is '_LC8_B13', type is buried
_LC8_B13 = LCELL( _EQ003);
_EQ003 = !CP_T & LDR4;
-- Node name is '|fuheys:29|:9'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = LCELL( _EQ004);
_EQ004 = !CP_T & LDR5;
-- Node name is '|fuheys:29|74181:46|:78' = '|fuheys:29|74181:46|CN4'
-- Equation name is '_LC5_B9', type is buried
_LC5_B9 = LCELL( _EQ005);
_EQ005 = _LC2_B9 & !_LC8_B4
# _LC1_B9;
-- Node name is '|fuheys:29|74181:46|:43'
-- Equation name is '_LC7_B9', type is buried
_LC7_B9 = LCELL( _EQ006);
_EQ006 = !_LC4_B6 & !s0 & !s1
# !_LC4_B6 & _LC5_B6 & !s0
# !_LC4_B6 & !_LC5_B6 & !s1;
-- Node name is '|fuheys:29|74181:46|:44'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ007);
_EQ007 = !_LC7_B11 & !s0 & !s1
# !_LC7_B11 & _LC8_B11 & !s0
# !_LC7_B11 & !_LC8_B11 & !s1;
-- Node name is '|fuheys:29|74181:46|:45'
-- Equation name is '_LC1_B4', type is buried
!_LC1_B4 = _LC1_B4~NOT;
_LC1_B4~NOT = LCELL( _EQ008);
_EQ008 = _LC7_B6
# !_LC6_B6 & s1
# _LC6_B6 & s0;
-- Node name is '|fuheys:29|74181:46|:46'
-- Equation name is '_LC6_B9', type is buried
_LC6_B9 = LCELL( _EQ009);
_EQ009 = !_LC4_B6
# _LC5_B6 & !s3
# !_LC5_B6 & !s2;
-- Node name is '|fuheys:29|74181:46|:47'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = LCELL( _EQ010);
_EQ010 = !_LC7_B11
# _LC8_B11 & !s3
# !_LC8_B11 & !s2;
-- Node name is '|fuheys:29|74181:46|:48'
-- Equation name is '_LC2_B4', type is buried
!_LC2_B4 = _LC2_B4~NOT;
_LC2_B4~NOT = LCELL( _EQ011);
_EQ011 = _LC7_B6 & s2 & s3
# _LC6_B6 & _LC7_B6 & s3
# !_LC6_B6 & _LC7_B6 & s2;
-- Node name is '|fuheys:29|74181:46|:51'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = LCELL( _EQ012);
_EQ012 = !_LC3_B9 & _LC4_B9 & !s0
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