📄 databusjiben.rpt
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Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 32/1152 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 8 8 7 8 7 8 7 0 8 8 8 8 8 8 2 6 0 0 2 0 0 8 8 8 0 127/8
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
Total: 8 8 7 8 7 8 7 0 8 8 9 8 8 8 2 6 0 0 2 0 0 8 8 8 0 128/8
Device-Specific Information: e:\xyq\maxplus\sy4\databusjiben.rpt
databusjiben
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
82 - - E -- INPUT 0 0 0 9 ALU_BUS
55 - - - -- INPUT G 0 0 0 1 clk_cdu
128 - - - 13 INPUT 0 0 0 2 CN
48 - - - 15 INPUT 0 0 0 1 cpldar
62 - - - 11 INPUT 0 0 0 4 CP_T
9 - - B -- BIDIR 0 1 0 7 dout0
10 - - B -- BIDIR 0 1 0 7 dout1
98 - - B -- BIDIR 0 1 0 7 dout2
51 - - - 14 BIDIR 0 1 0 7 dout3
96 - - B -- BIDIR 0 1 0 7 dout4
99 - - B -- BIDIR 0 1 0 7 dout5
97 - - B -- BIDIR 0 1 0 7 dout6
95 - - B -- BIDIR 0 1 0 7 dout7
117 - - - 05 INPUT 0 0 0 2 enable
136 - - - 20 INPUT 0 0 0 1 inputd0
47 - - - 16 INPUT 0 0 0 1 inputd1
119 - - - 07 INPUT 0 0 0 1 inputd2
135 - - - 19 INPUT 0 0 0 1 inputd3
110 - - - 01 INPUT 0 0 0 1 inputd4
63 - - - 10 INPUT 0 0 0 1 inputd5
114 - - - 04 INPUT 0 0 0 1 inputd6
113 - - - 03 INPUT 0 0 0 1 inputd7
141 - - - 23 INPUT 0 0 0 1 LDAR
120 - - - 08 INPUT 0 0 0 1 LDDR1
116 - - - 04 INPUT 0 0 0 1 LDDR2
43 - - - 18 INPUT 0 0 0 1 LDR4
137 - - - 20 INPUT 0 0 0 1 LDR5
125 - - - -- INPUT 0 0 0 8 M
42 - - - 19 INPUT 0 0 0 9 pc_bus
124 - - - -- INPUT 0 0 0 10 RD
56 - - - -- INPUT 0 0 0 9 R4_BUS
126 - - - -- INPUT 0 0 0 9 R5_BUS
121 - - - 10 INPUT 0 0 0 2 sw_bus
67 - - - 08 INPUT 0 0 0 8 s0
69 - - - 06 INPUT 0 0 0 8 s1
65 - - - 09 INPUT 0 0 0 8 s2
111 - - - 01 INPUT 0 0 0 8 s3
49 - - - 14 INPUT 0 0 0 1 WE
54 - - - -- INPUT G 0 0 0 0 161clr
68 - - - 07 INPUT 0 0 0 8 161load
81 - - F -- INPUT 0 0 0 1 161pc
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\xyq\maxplus\sy4\databusjiben.rpt
databusjiben
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
138 - - - 21 OUTPUT 0 1 0 0 adr0
13 - - C -- OUTPUT 0 1 0 0 adr1
20 - - D -- OUTPUT 0 1 0 0 adr2
39 - - - 21 OUTPUT 0 1 0 0 adr3
140 - - - 22 OUTPUT 0 1 0 0 adr4
7 - - A -- OUTPUT 0 1 0 0 adr5
19 - - D -- OUTPUT 0 1 0 0 adr6
38 - - - 22 OUTPUT 0 1 0 0 adr7
64 - - - 09 OUTPUT 0 1 0 0 cn4
9 - - B -- TRI 0 1 0 7 dout0
10 - - B -- TRI 0 1 0 7 dout1
98 - - B -- TRI 0 1 0 7 dout2
51 - - - 14 TRI 0 1 0 7 dout3
96 - - B -- TRI 0 1 0 7 dout4
99 - - B -- TRI 0 1 0 7 dout5
97 - - B -- TRI 0 1 0 7 dout6
95 - - B -- TRI 0 1 0 7 dout7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\xyq\maxplus\sy4\databusjiben.rpt
databusjiben
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 06 AND2 2 0 0 8 |fuheys:29|:6
- 2 - B 06 AND2 2 0 0 8 |fuheys:29|:7
- 8 - B 13 AND2 2 0 0 8 |fuheys:29|:8
- 5 - B 13 AND2 2 0 0 8 |fuheys:29|:9
- 7 - B 09 OR2 2 2 0 2 |fuheys:29|74181:46|:43
- 4 - B 11 OR2 2 2 0 2 |fuheys:29|74181:46|:44
- 1 - B 04 OR2 ! 2 2 0 2 |fuheys:29|74181:46|:45
- 6 - B 09 OR2 2 2 0 2 |fuheys:29|74181:46|:46
- 2 - B 11 OR2 2 2 0 2 |fuheys:29|74181:46|:47
- 2 - B 04 OR2 ! 2 2 0 2 |fuheys:29|74181:46|:48
- 1 - B 09 OR2 2 2 0 2 |fuheys:29|74181:46|:51
- 2 - B 09 OR2 2 2 0 2 |fuheys:29|74181:46|:52
- 8 - B 04 OR2 s 0 3 0 2 |fuheys:29|74181:46|~74~1
- 2 - B 03 OR2 s 0 3 0 2 |fuheys:29|74181:46|~75~1
- 8 - B 09 OR2 1 3 0 1 |fuheys:29|74181:46|:77
- 5 - B 09 OR2 0 3 1 0 |fuheys:29|74181:46|CN4 (|fuheys:29|74181:46|:78)
- 4 - B 01 OR2 s 0 3 0 2 |fuheys:29|74181:46|~79~1
- 6 - B 01 OR2 1 3 0 1 |fuheys:29|74181:46|:80
- 4 - B 03 OR2 1 3 0 1 |fuheys:29|74181:46|:81
- 5 - B 04 OR2 1 3 0 1 |fuheys:29|74181:46|:82
- 2 - B 12 OR2 ! 2 2 0 2 |fuheys:29|74181:47|:43
- 3 - B 12 OR2 ! 2 2 0 2 |fuheys:29|74181:47|:44
- 1 - B 11 OR2 ! 2 2 0 2 |fuheys:29|74181:47|:45
- 1 - B 12 OR2 ! 2 2 0 2 |fuheys:29|74181:47|:46
- 8 - B 12 OR2 ! 2 2 0 2 |fuheys:29|74181:47|:47
- 6 - B 11 OR2 ! 2 2 0 2 |fuheys:29|74181:47|:48
- 2 - B 01 OR2 ! 2 2 0 2 |fuheys:29|74181:47|:51
- 5 - B 01 OR2 ! 2 2 0 2 |fuheys:29|74181:47|:52
- 7 - B 01 OR2 1 3 0 1 |fuheys:29|74181:47|:77
- 3 - B 21 OR2 s 0 3 0 2 |fuheys:29|74181:47|CN4~1 (|fuheys:29|74181:47|~78~1)
- 1 - B 01 OR2 s 0 3 0 2 |fuheys:29|74181:47|CN4~2 (|fuheys:29|74181:47|~78~2)
- 8 - B 01 OR2 ! 0 3 0 2 |fuheys:29|74181:47|CN4 (|fuheys:29|74181:47|:78)
- 2 - B 15 OR2 s 1 2 0 2 |fuheys:29|74181:47|~79~1
- 5 - B 15 OR2 2 2 0 1 |fuheys:29|74181:47|:80
- 4 - B 21 OR2 1 3 0 1 |fuheys:29|74181:47|:81
- 3 - B 01 OR2 1 3 0 1 |fuheys:29|74181:47|:82
- 4 - B 09 DFFE 0 2 0 2 |fuheys:29|74273:44|Q8 (|fuheys:29|74273:44|:12)
- 6 - B 06 DFFE 0 2 0 2 |fuheys:29|74273:44|Q7 (|fuheys:29|74273:44|:13)
- 8 - B 11 DFFE 0 2 0 2 |fuheys:29|74273:44|Q6 (|fuheys:29|74273:44|:14)
- 5 - B 06 DFFE 0 2 0 2 |fuheys:29|74273:44|Q5 (|fuheys:29|74273:44|:15)
- 8 - B 06 DFFE 0 2 0 2 |fuheys:29|74273:44|Q4 (|fuheys:29|74273:44|:16)
- 5 - B 11 DFFE 0 2 0 2 |fuheys:29|74273:44|Q3 (|fuheys:29|74273:44|:17)
- 5 - B 12 DFFE 0 2 0 2 |fuheys:29|74273:44|Q2 (|fuheys:29|74273:44|:18)
- 7 - B 12 DFFE 0 2 0 2 |fuheys:29|74273:44|Q1 (|fuheys:29|74273:44|:19)
- 3 - B 09 DFFE 0 2 0 2 |fuheys:29|74273:45|Q8 (|fuheys:29|74273:45|:12)
- 7 - B 06 DFFE 0 2 0 2 |fuheys:29|74273:45|Q7 (|fuheys:29|74273:45|:13)
- 7 - B 11 DFFE 0 2 0 2 |fuheys:29|74273:45|Q6 (|fuheys:29|74273:45|:14)
- 4 - B 06 DFFE 0 2 0 2 |fuheys:29|74273:45|Q5 (|fuheys:29|74273:45|:15)
- 1 - B 06 DFFE 0 2 0 2 |fuheys:29|74273:45|Q4 (|fuheys:29|74273:45|:16)
- 3 - B 11 DFFE 0 2 0 2 |fuheys:29|74273:45|Q3 (|fuheys:29|74273:45|:17)
- 4 - B 12 DFFE 0 2 0 2 |fuheys:29|74273:45|Q2 (|fuheys:29|74273:45|:18)
- 6 - B 12 DFFE 0 2 0 2 |fuheys:29|74273:45|Q1 (|fuheys:29|74273:45|:19)
- 7 - B 05 DFFE 0 2 0 1 |fuheys:29|74374:42|:13
- 8 - B 21 DFFE 0 2 0 1 |fuheys:29|74374:42|:14
- 3 - B 05 DFFE 0 2 0 1 |fuheys:29|74374:42|:15
- 7 - B 13 DFFE 0 2 0 1 |fuheys:29|74374:42|:16
- 7 - B 07 DFFE 0 2 0 1 |fuheys:29|74374:42|:17
- 7 - B 03 DFFE 0 2 0 1 |fuheys:29|74374:42|:18
- 7 - B 04 DFFE 0 2 0 1 |fuheys:29|74374:42|:19
- 3 - B 13 DFFE 0 2 0 1 |fuheys:29|74374:42|:20
- 5 - B 05 DFFE 0 2 0 1 |fuheys:29|74374:43|:13
- 7 - B 21 DFFE 0 2 0 1 |fuheys:29|74374:43|:14
- 2 - B 05 DFFE 0 2 0 1 |fuheys:29|74374:43|:15
- 4 - B 13 DFFE 0 2 0 1 |fuheys:29|74374:43|:16
- 4 - B 05 DFFE 0 2 0 1 |fuheys:29|74374:43|:17
- 6 - B 03 DFFE 0 2 0 1 |fuheys:29|74374:43|:18
- 4 - B 18 DFFE 0 2 0 1 |fuheys:29|74374:43|:19
- 1 - B 13 DFFE 0 2 0 1 |fuheys:29|74374:43|:20
- - 2 B -- MEM_SGMT 0 10 0 1 |shiyan3jiben:1|LPM_RAM_IO:50|altram:sram|segment0_0
- - 1 B -- MEM_SGMT 0 10 0 1 |shiyan3jiben:1|LPM_RAM_IO:50|altram:sram|segment0_1
- - 6 B -- MEM_SGMT 0 10 0 1 |shiyan3jiben:1|LPM_RAM_IO:50|altram:sram|segment0_2
- - 7 B -- MEM_SGMT 0 10 0 1 |shiyan3jiben:1|LPM_RAM_IO:50|altram:sram|segment0_3
- - 4 B -- MEM_SGMT 0 10 0 1 |shiyan3jiben:1|LPM_RAM_IO:50|altram:sram|segment0_4
- - 3 B -- MEM_SGMT 0 10 0 1 |shiyan3jiben:1|LPM_RAM_IO:50|altram:sram|segment0_5
- - 8 B -- MEM_SGMT 0 10 0 1 |shiyan3jiben:1|LPM_RAM_IO:50|altram:sram|segment0_6
- - 5 B -- MEM_SGMT 0 10 0 1 |shiyan3jiben:1|LPM_RAM_IO:50|altram:sram|segment0_7
- 1 - B 15 AND2 2 0 0 8 |shiyan3jiben:1|LPM_RAM_IO:50|:90
- 1 - B 22 AND2 2 0 0 8 |shiyan3jiben:1|:27
- 2 - F 11 AND2 2 0 0 8 |shiyan3jiben:1|:32
- 4 - B 23 DFFE 1 2 0 5 |shiyan3jiben:1|74161:2|f74161:sub|QA (|shiyan3jiben:1|74161:2|f74161:sub|:9)
- 1 - B 23 AND2 0 2 0 1 |shiyan3jiben:1|74161:2|f74161:sub|:84
- 6 - B 23 DFFE 1 3 0 4 |shiyan3jiben:1|74161:2|f74161:sub|QB (|shiyan3jiben:1|74161:2|f74161:sub|:87)
- 3 - B 23 AND2 0 3 0 1 |shiyan3jiben:1|74161:2|f74161:sub|:94
- 7 - B 23 DFFE 1 3 0 3 |shiyan3jiben:1|74161:2|f74161:sub|QC (|shiyan3jiben:1|74161:2|f74161:sub|:99)
- 5 - B 23 AND2 0 4 0 2 |shiyan3jiben:1|74161:2|f74161:sub|:104
- 8 - B 23 DFFE 1 3 0 2 |shiyan3jiben:1|74161:2|f74161:sub|QD (|shiyan3jiben:1|74161:2|f74161:sub|:110)
- 4 - B 07 DFFE 1 3 0 2 |shiyan3jiben:1|74161:3|f74161:sub|QA (|shiyan3jiben:1|74161:3|f74161:sub|:9)
- 5 - B 07 AND2 0 2 0 2 |shiyan3jiben:1|74161:3|f74161:sub|:80
- 1 - B 02 AND2 0 2 0 2 |shiyan3jiben:1|74161:3|f74161:sub|:84
- 5 - B 02 DFFE 1 3 0 2 |shiyan3jiben:1|74161:3|f74161:sub|QB (|shiyan3jiben:1|74161:3|f74161:sub|:87)
- 3 - B 02 AND2 0 2 0 1 |shiyan3jiben:1|74161:3|f74161:sub|:94
- 7 - B 02 DFFE 1 3 0 2 |shiyan3jiben:1|74161:3|f74161:sub|QC (|shiyan3jiben:1|74161:3|f74161:sub|:99)
- 4 - B 02 DFFE 1 3 0 1 |shiyan3jiben:1|74161:3|f74161:sub|QD (|shiyan3jiben:1|74161:3|f74161:sub|:110)
- 3 - B 10 OR2 s 4 0 0 1 |shiyan3jiben:1|74244:4|~1~1~2~2~2
- 4 - B 10 OR2 3 1 0 0 |shiyan3jiben:1|74244:4|~1~1~2~2
- 2 - B 10 OR2 s 2 0 0 8 |shiyan3jiben:1|74244:4|~1~1~2~3~3
- 3 - B 15 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~1~1~2~3~4
- 1 - B 05 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~1~1~2~3~5
- 6 - B 15 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~1~1~2~3~6
- 4 - B 15 AND2 0 3 1 0 |shiyan3jiben:1|74244:4|~1~1~2~3
- 1 - B 21 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~6~1~2~3~3
- 2 - B 21 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~6~1~2~3~4
- 6 - B 21 OR2 s 1 3 0 1 |shiyan3jiben:1|74244:4|~6~1~2~3~5
- 5 - B 21 OR2 1 2 1 0 |shiyan3jiben:1|74244:4|~6~1~2~3
- 5 - B 10 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~10~1~2~3~3
- 6 - B 05 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~10~1~2~3~4
- 6 - B 10 OR2 s 1 3 0 1 |shiyan3jiben:1|74244:4|~10~1~2~3~5
- 1 - B 10 OR2 1 2 1 0 |shiyan3jiben:1|74244:4|~10~1~2~3
- 2 - B 23 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~11~1~2~3~3
- 2 - B 13 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~11~1~2~3~4
- 2 - B 14 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~11~1~2~3~5
- 1 - B 14 AND2 0 3 1 0 |shiyan3jiben:1|74244:4|~11~1~2~3
- 8 - B 02 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~26~1~2~3~3
- 6 - B 13 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~26~1~2~3~4
- 8 - B 10 OR2 s 1 3 0 1 |shiyan3jiben:1|74244:4|~26~1~2~3~5
- 7 - B 10 OR2 1 2 1 0 |shiyan3jiben:1|74244:4|~26~1~2~3
- 2 - B 02 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~27~1~2~3~3
- 3 - B 04 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~27~1~2~3~4
- 6 - B 04 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~27~1~2~3~5
- 4 - B 04 AND2 0 3 1 0 |shiyan3jiben:1|74244:4|~27~1~2~3
- 6 - B 02 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~31~1~2~3~3
- 3 - B 03 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~31~1~2~3~4
- 5 - B 03 OR2 s 1 3 0 1 |shiyan3jiben:1|74244:4|~31~1~2~3~5
- 1 - B 03 OR2 1 2 1 0 |shiyan3jiben:1|74244:4|~31~1~2~3
- 1 - B 07 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~36~1~2~3~3
- 2 - B 07 OR2 s 2 2 0 1 |shiyan3jiben:1|74244:4|~36~1~2~3~4
- 3 - B 07 OR2 s 1 3 0 1 |shiyan3jiben:1|74244:4|~36~1~2~3~5
- 6 - B 07 OR2 1 2 1 0 |shiyan3jiben:1|74244:4|~36~1~2~3
- 6 - B 22 DFFE 0 2 1 8 |shiyan3jiben:1|74273:5|Q8 (|shiyan3jiben:1|74273:5|:12)
- 3 - B 18 DFFE 0 2 1 8 |shiyan3jiben:1|74273:5|Q7 (|shiyan3jiben:1|74273:5|:13)
- 7 - B 22 DFFE 0 2 1 8 |shiyan3jiben:1|74273:5|Q6 (|shiyan3jiben:1|74273:5|:14)
- 8 - B 22 DFFE 0 2 1 8 |shiyan3jiben:1|74273:5|Q5 (|shiyan3jiben:1|74273:5|:15)
- 3 - B 22 DFFE 0 2 1 8 |shiyan3jiben:1|74273:5|Q4 (|shiyan3jiben:1|74273:5|:16)
- 4 - B 22 DFFE 0 2 1 8 |shiyan3jiben:1|74273:5|Q3 (|shiyan3jiben:1|74273:5|:17)
- 2 - B 22 DFFE 0 2 1 8 |shiyan3jiben:1|74273:5|Q2 (|shiyan3jiben:1|74273:5|:18)
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