📄 shiyan3jiben.rpt
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# _LC3_D16 & !_LC5_D16 & 161load;
-- Node name is '|74161:3|f74161:sub|:80'
-- Equation name is '_LC4_D24', type is buried
_LC4_D24 = LCELL( _EQ013);
_EQ013 = _LC7_D15 & _LC8_D24;
-- Node name is '|74161:3|f74161:sub|:84'
-- Equation name is '_LC3_D24', type is buried
_LC3_D24 = LCELL( _EQ014);
_EQ014 = _LC4_D24 & _LC7_D24;
-- Node name is '|74161:3|f74161:sub|:94'
-- Equation name is '_LC3_D16', type is buried
_LC3_D16 = LCELL( _EQ015);
_EQ015 = _LC3_D24 & _LC8_D16;
-- Node name is '|74244:4|~1~1~2'
-- Equation name is '_LC1_D24', type is buried
_LC1_D24 = LCELL( _EQ016);
_EQ016 = MEMENAB & RD
# !pc_bus
# sw_bus;
-- Node name is '|74244:4|~1~1~3~2'
-- Equation name is '_LC8_D15', type is buried
-- synthesized logic cell
_LC8_D15 = LCELL( _EQ017);
_EQ017 = pc_bus & !sw_bus
# _LC4_D15 & !sw_bus
# inputd0 & pc_bus
# inputd0 & _LC4_D15;
-- Node name is '|74244:4|~1~1~3'
-- Equation name is '_LC5_D15', type is buried
_LC5_D15 = LCELL( _EQ018);
_EQ018 = _EC1_D & _LC8_D15
# _LC8_D15 & !MEMENAB
# _LC8_D15 & !RD;
-- Node name is '|74244:4|~6~1~3~2'
-- Equation name is '_LC7_D17', type is buried
-- synthesized logic cell
_LC7_D17 = LCELL( _EQ019);
_EQ019 = pc_bus & !sw_bus
# _LC8_D17 & !sw_bus
# inputd1 & pc_bus
# inputd1 & _LC8_D17;
-- Node name is '|74244:4|~6~1~3'
-- Equation name is '_LC4_D17', type is buried
_LC4_D17 = LCELL( _EQ020);
_EQ020 = _EC5_D & _LC7_D17
# _LC7_D17 & !MEMENAB
# _LC7_D17 & !RD;
-- Node name is '|74244:4|~10~1~3~2'
-- Equation name is '_LC1_D17', type is buried
-- synthesized logic cell
_LC1_D17 = LCELL( _EQ021);
_EQ021 = pc_bus & !sw_bus
# _LC6_D17 & !sw_bus
# inputd2 & pc_bus
# inputd2 & _LC6_D17;
-- Node name is '|74244:4|~10~1~3'
-- Equation name is '_LC2_D17', type is buried
_LC2_D17 = LCELL( _EQ022);
_EQ022 = _EC6_D & _LC1_D17
# _LC1_D17 & !MEMENAB
# _LC1_D17 & !RD;
-- Node name is '|74244:4|~11~1~3~2'
-- Equation name is '_LC1_D15', type is buried
-- synthesized logic cell
_LC1_D15 = LCELL( _EQ023);
_EQ023 = pc_bus & !sw_bus
# _LC2_D15 & !sw_bus
# inputd3 & pc_bus
# inputd3 & _LC2_D15;
-- Node name is '|74244:4|~11~1~3'
-- Equation name is '_LC3_D15', type is buried
_LC3_D15 = LCELL( _EQ024);
_EQ024 = _EC2_D & _LC1_D15
# _LC1_D15 & !MEMENAB
# _LC1_D15 & !RD;
-- Node name is '|74244:4|~26~1~3~2'
-- Equation name is '_LC2_D16', type is buried
-- synthesized logic cell
_LC2_D16 = LCELL( _EQ025);
_EQ025 = pc_bus & !sw_bus
# _LC5_D16 & !sw_bus
# inputd7 & pc_bus
# inputd7 & _LC5_D16;
-- Node name is '|74244:4|~26~1~3'
-- Equation name is '_LC4_D16', type is buried
_LC4_D16 = LCELL( _EQ026);
_EQ026 = _EC8_D & _LC2_D16
# _LC2_D16 & !MEMENAB
# _LC2_D16 & !RD;
-- Node name is '|74244:4|~27~1~3~2'
-- Equation name is '_LC7_D16', type is buried
-- synthesized logic cell
_LC7_D16 = LCELL( _EQ027);
_EQ027 = pc_bus & !sw_bus
# _LC8_D16 & !sw_bus
# inputd6 & pc_bus
# inputd6 & _LC8_D16;
-- Node name is '|74244:4|~27~1~3'
-- Equation name is '_LC1_D16', type is buried
_LC1_D16 = LCELL( _EQ028);
_EQ028 = _EC7_D & _LC7_D16
# _LC7_D16 & !MEMENAB
# _LC7_D16 & !RD;
-- Node name is '|74244:4|~31~1~3~2'
-- Equation name is '_LC5_D24', type is buried
-- synthesized logic cell
_LC5_D24 = LCELL( _EQ029);
_EQ029 = pc_bus & !sw_bus
# _LC7_D24 & !sw_bus
# inputd5 & pc_bus
# inputd5 & _LC7_D24;
-- Node name is '|74244:4|~31~1~3'
-- Equation name is '_LC6_D24', type is buried
_LC6_D24 = LCELL( _EQ030);
_EQ030 = _EC3_D & _LC5_D24
# _LC5_D24 & !MEMENAB
# _LC5_D24 & !RD;
-- Node name is '|74244:4|~36~1~3~2'
-- Equation name is '_LC2_D24', type is buried
-- synthesized logic cell
_LC2_D24 = LCELL( _EQ031);
_EQ031 = pc_bus & !sw_bus
# _LC8_D24 & !sw_bus
# inputd4 & pc_bus
# inputd4 & _LC8_D24;
-- Node name is '|74244:4|~36~1~3'
-- Equation name is '_LC6_D16', type is buried
_LC6_D16 = LCELL( _EQ032);
_EQ032 = _EC4_D & _LC2_D24
# _LC2_D24 & !MEMENAB
# _LC2_D24 & !RD;
-- Node name is '|74273:5|:19' = '|74273:5|Q1'
-- Equation name is '_LC6_D15', type is buried
_LC6_D15 = DFFE( d0, _LC8_D2, VCC, VCC, VCC);
-- Node name is '|74273:5|:18' = '|74273:5|Q2'
-- Equation name is '_LC6_D2', type is buried
_LC6_D2 = DFFE( d1, _LC8_D2, VCC, VCC, VCC);
-- Node name is '|74273:5|:17' = '|74273:5|Q3'
-- Equation name is '_LC1_D2', type is buried
_LC1_D2 = DFFE( d2, _LC8_D2, VCC, VCC, VCC);
-- Node name is '|74273:5|:16' = '|74273:5|Q4'
-- Equation name is '_LC2_D2', type is buried
_LC2_D2 = DFFE( d3, _LC8_D2, VCC, VCC, VCC);
-- Node name is '|74273:5|:15' = '|74273:5|Q5'
-- Equation name is '_LC3_D2', type is buried
_LC3_D2 = DFFE( d4, _LC8_D2, VCC, VCC, VCC);
-- Node name is '|74273:5|:14' = '|74273:5|Q6'
-- Equation name is '_LC4_D2', type is buried
_LC4_D2 = DFFE( d5, _LC8_D2, VCC, VCC, VCC);
-- Node name is '|74273:5|:13' = '|74273:5|Q7'
-- Equation name is '_LC5_D2', type is buried
_LC5_D2 = DFFE( d6, _LC8_D2, VCC, VCC, VCC);
-- Node name is '|74273:5|:12' = '|74273:5|Q8'
-- Equation name is '_LC7_D2', type is buried
_LC7_D2 = DFFE( d7, _LC8_D2, VCC, VCC, VCC);
-- Node name is ':27'
-- Equation name is '_LC8_D2', type is buried
_LC8_D2 = LCELL( _EQ033);
_EQ033 = !cp161ldar & LDAR;
-- Node name is ':32'
-- Equation name is '_LC5_F21', type is buried
_LC5_F21 = LCELL( _EQ034);
_EQ034 = clk_cdu & 161pc;
-- Node name is '|LPM_RAM_IO:50|altram:sram|segment0_0' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC1_D', type is memory
_EC1_D = MEMORY_SEGMENT( d0, GLOBAL( clk_cdu), VCC, _LC1_D12, VCC, _LC6_D15, _LC6_D2, _LC1_D2, _LC2_D2, _LC3_D2, _LC4_D2, _LC5_D2, _LC7_D2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:50|altram:sram|segment0_1' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC5_D', type is memory
_EC5_D = MEMORY_SEGMENT( d1, GLOBAL( clk_cdu), VCC, _LC1_D12, VCC, _LC6_D15, _LC6_D2, _LC1_D2, _LC2_D2, _LC3_D2, _LC4_D2, _LC5_D2, _LC7_D2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:50|altram:sram|segment0_2' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC6_D', type is memory
_EC6_D = MEMORY_SEGMENT( d2, GLOBAL( clk_cdu), VCC, _LC1_D12, VCC, _LC6_D15, _LC6_D2, _LC1_D2, _LC2_D2, _LC3_D2, _LC4_D2, _LC5_D2, _LC7_D2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:50|altram:sram|segment0_3' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC2_D', type is memory
_EC2_D = MEMORY_SEGMENT( d3, GLOBAL( clk_cdu), VCC, _LC1_D12, VCC, _LC6_D15, _LC6_D2, _LC1_D2, _LC2_D2, _LC3_D2, _LC4_D2, _LC5_D2, _LC7_D2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:50|altram:sram|segment0_4' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC4_D', type is memory
_EC4_D = MEMORY_SEGMENT( d4, GLOBAL( clk_cdu), VCC, _LC1_D12, VCC, _LC6_D15, _LC6_D2, _LC1_D2, _LC2_D2, _LC3_D2, _LC4_D2, _LC5_D2, _LC7_D2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:50|altram:sram|segment0_5' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC3_D', type is memory
_EC3_D = MEMORY_SEGMENT( d5, GLOBAL( clk_cdu), VCC, _LC1_D12, VCC, _LC6_D15, _LC6_D2, _LC1_D2, _LC2_D2, _LC3_D2, _LC4_D2, _LC5_D2, _LC7_D2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:50|altram:sram|segment0_6' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC7_D', type is memory
_EC7_D = MEMORY_SEGMENT( d6, GLOBAL( clk_cdu), VCC, _LC1_D12, VCC, _LC6_D15, _LC6_D2, _LC1_D2, _LC2_D2, _LC3_D2, _LC4_D2, _LC5_D2, _LC7_D2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:50|altram:sram|segment0_7' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC8_D', type is memory
_EC8_D = MEMORY_SEGMENT( d7, GLOBAL( clk_cdu), VCC, _LC1_D12, VCC, _LC6_D15, _LC6_D2, _LC1_D2, _LC2_D2, _LC3_D2, _LC4_D2, _LC5_D2, _LC7_D2, VCC, VCC, VCC,);
Project Information e:\xyq\maxplus\sy4\shiyan3jiben.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,883K
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