📄 fuheys.rpt
字号:
(27) 43 C DFFE t 0 0 0 2 1 1 0 |74374:42|:18
- 44 C DFFE t 0 0 0 2 1 1 0 |74374:42|:19
(25) 45 C DFFE t 0 0 0 2 1 1 0 |74374:42|:20
(18) 25 B DFFE t 0 0 0 2 1 1 0 |74374:43|:13
- 26 B DFFE t 0 0 0 2 1 1 0 |74374:43|:14
(17) 27 B DFFE t 0 0 0 2 1 1 0 |74374:43|:15
- 31 B DFFE t 0 0 0 2 1 1 0 |74374:43|:16
(33) 33 C DFFE t 0 0 0 2 1 1 0 |74374:43|:17
- 36 C DFFE t 0 0 0 2 1 1 0 |74374:43|:18
(30) 37 C DFFE t 0 0 0 2 1 1 0 |74374:43|:19
- 38 C DFFE t 0 0 0 2 1 1 0 |74374:43|:20
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\xyq\maxplus\sy4\fuheys.rpt
fuheys
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC21 |74273:44|Q4
| +----------------------------- LC20 |74273:44|Q3
| | +--------------------------- LC24 |74273:44|Q2
| | | +------------------------- LC22 |74273:44|Q1
| | | | +----------------------- LC28 |74273:45|Q4
| | | | | +--------------------- LC30 |74273:45|Q3
| | | | | | +------------------- LC32 |74273:45|Q2
| | | | | | | +----------------- LC29 |74273:45|Q1
| | | | | | | | +--------------- LC23 |74374:42|:13
| | | | | | | | | +------------- LC19 |74374:42|:14
| | | | | | | | | | +----------- LC18 |74374:42|:15
| | | | | | | | | | | +--------- LC17 |74374:42|:16
| | | | | | | | | | | | +------- LC25 |74374:43|:13
| | | | | | | | | | | | | +----- LC26 |74374:43|:14
| | | | | | | | | | | | | | +--- LC27 |74374:43|:15
| | | | | | | | | | | | | | | +- LC31 |74374:43|:16
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'B':
Pin
22 -> * * * * * * * * * * * * * * * * | - * * - - - | <-- cp_t
15 -> - - - - * * * * - - - - - - - - | - * * - - - | <-- LDDR1
9 -> * * * * - - - - - - - - - - - - | - * * - - - | <-- LDDR2
10 -> - - - - - - - - - - - - * * * * | - * * - - - | <-- LDR4
13 -> - - - - - - - - * * * * - - - - | - * * - - - | <-- LDR5
68 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN001
LC56 -> - - - * - - - * * - - - * - - - | - * - - - - | <-- D0
LC53 -> - - * - - - * - - * - - - * - - | - * - - - - | <-- D1
LC49 -> - * - - - * - - - - * - - - * - | - * - - - - | <-- D2
LC61 -> * - - - * - - - - - - * - - - * | - * - - - - | <-- D3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\xyq\maxplus\sy4\fuheys.rpt
fuheys
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC40 |74273:44|Q8
| +----------------------------- LC41 |74273:44|Q7
| | +--------------------------- LC35 |74273:44|Q6
| | | +------------------------- LC34 |74273:44|Q5
| | | | +----------------------- LC48 |74273:45|Q8
| | | | | +--------------------- LC47 |74273:45|Q7
| | | | | | +------------------- LC39 |74273:45|Q6
| | | | | | | +----------------- LC46 |74273:45|Q5
| | | | | | | | +--------------- LC42 |74374:42|:17
| | | | | | | | | +------------- LC43 |74374:42|:18
| | | | | | | | | | +----------- LC44 |74374:42|:19
| | | | | | | | | | | +--------- LC45 |74374:42|:20
| | | | | | | | | | | | +------- LC33 |74374:43|:17
| | | | | | | | | | | | | +----- LC36 |74374:43|:18
| | | | | | | | | | | | | | +--- LC37 |74374:43|:19
| | | | | | | | | | | | | | | +- LC38 |74374:43|:20
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'C':
Pin
22 -> * * * * * * * * * * * * * * * * | - * * - - - | <-- cp_t
15 -> - - - - * * * * - - - - - - - - | - * * - - - | <-- LDDR1
9 -> * * * * - - - - - - - - - - - - | - * * - - - | <-- LDDR2
10 -> - - - - - - - - - - - - * * * * | - * * - - - | <-- LDR4
13 -> - - - - - - - - * * * * - - - - | - * * - - - | <-- LDR5
68 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN001
LC64 -> - - - * - - - * * - - - * - - - | - - * - - - | <-- D4
LC51 -> - - * - - - * - - * - - - * - - | - - * - - - | <-- D5
LC57 -> - * - - - * - - - - * - - - * - | - - * - - - | <-- D6
LC59 -> * - - - * - - - - - - * - - - * | - - * - - - | <-- D7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\xyq\maxplus\sy4\fuheys.rpt
fuheys
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+--------------- LC56 D0
| +------------- LC53 D1
| | +----------- LC49 D2
| | | +--------- LC61 D3
| | | | +------- LC64 D4
| | | | | +----- LC51 D5
| | | | | | +--- LC57 D6
| | | | | | | +- LC59 D7
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'D'
LC | | | | | | | | | A B C D E F | Logic cells that feed LAB 'D':
Pin
8 -> * * * * * * * * | - - - * * - | <-- ALU_BUS
30 -> * - - - - - - - | - - - * - - | <-- in0
29 -> - * - - - - - - | - - - * - - | <-- in1
28 -> - - * - - - - - | - - - * - - | <-- in2
33 -> - - - * - - - - | - - - * - - | <-- in3
62 -> - - - - * - - - | - - - * - - | <-- in4
50 -> - - - - - * - - | - - - * - - | <-- in5
54 -> - - - - - - * - | - - - * - - | <-- in6
27 -> - - - - - - - * | - - - * - - | <-- in7
68 -> - - - - - - - - | - - - - - - | <-- ~PIN001
17 -> * * * * * * * * | - - - * * - | <-- R4_BUS
47 -> * * * * * * * * | - - - * * - | <-- R5_BUS
7 -> * * * * * * * * | - - - * * - | <-- SW_BUS
LC95 -> - - - - - - - * | - - - * - - | <-- |74181:46|F3N
LC86 -> - - - - - - * - | - - - * - - | <-- |74181:46|F2N
LC88 -> - - - - - * - - | - - - * - - | <-- |74181:46|F1N
LC78 -> - - - - * - - - | - - - * - - | <-- |74181:46|F0N
LC79 -> - - - * - - - - | - - - * - - | <-- |74181:47|F3N
LC77 -> - - * - - - - - | - - - * - - | <-- |74181:47|F2N
LC76 -> - * - - - - - - | - - - * - - | <-- |74181:47|F1N
LC85 -> * - - - - - - - | - - - * - - | <-- |74181:47|F0N
LC23 -> * - - - - - - - | - - - * - - | <-- |74374:42|:13
LC19 -> - * - - - - - - | - - - * - - | <-- |74374:42|:14
LC18 -> - - * - - - - - | - - - * - - | <-- |74374:42|:15
LC17 -> - - - * - - - - | - - - * - - | <-- |74374:42|:16
LC42 -> - - - - * - - - | - - - * - - | <-- |74374:42|:17
LC43 -> - - - - - * - - | - - - * - - | <-- |74374:42|:18
LC44 -> - - - - - - * - | - - - * - - | <-- |74374:42|:19
LC45 -> - - - - - - - * | - - - * - - | <-- |74374:42|:20
LC25 -> * - - - - - - - | - - - * - - | <-- |74374:43|:13
LC26 -> - * - - - - - - | - - - * - - | <-- |74374:43|:14
LC27 -> - - * - - - - - | - - - * - - | <-- |74374:43|:15
LC31 -> - - - * - - - - | - - - * - - | <-- |74374:43|:16
LC33 -> - - - - * - - - | - - - * - - | <-- |74374:43|:17
LC36 -> - - - - - * - - | - - - * - - | <-- |74374:43|:18
LC37 -> - - - - - - * - | - - - * - - | <-- |74374:43|:19
LC38 -> - - - - - - - * | - - - * - - | <-- |74374:43|:20
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\xyq\maxplus\sy4\fuheys.rpt
fuheys
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+------------------------------- LC69 ~PIN002
| +----------------------------- LC70 |74181:46|:37
| | +--------------------------- LC73 |74181:46|:38
| | | +------------------------- LC78 |74181:46|F0N
| | | | +----------------------- LC72 |74181:46|:88
| | | | | +--------------------- LC68 |74181:47|:37
| | | | | | +------------------- LC75 |74181:47|:38
| | | | | | | +----------------- LC80 |74181:47|:39
| | | | | | | | +--------------- LC67 |74181:47|:40
| | | | | | | | | +------------- LC66 |74181:47|:41
| | | | | | | | | | +----------- LC65 |74181:47|:42
| | | | | | | | | | | +--------- LC74 |74181:47|:49
| | | | | | | | | | | | +------- LC71 |74181:47|:50
| | | | | | | | | | | | | +----- LC79 |74181:47|F3N
| | | | | | | | | | | | | | +--- LC77 |74181:47|F2N
| | | | | | | | | | | | | | | +- LC76 |74181:47|F1N
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'E'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'E':
LC70 -> - - - * * - - - - - - - - - - - | - - - - * * | <-- |74181:46|:37
LC73 -> - - - * * - - - - - - - - - - - | - - - - * * | <-- |74181:46|:38
LC68 -> - - - * * - - - - - - - - - - - | - - - - * * | <-- |74181:47|:37
LC75 -> - - - * * - - - - - - - - - - - | - - - - * * | <-- |74181:47|:38
LC80 -> - - - * * - - - - - - - - - - * | - - - - * * | <-- |74181:47|:39
LC67 -> - - - * * - - - - - - - - - - * | - - - - * * | <-- |74181:47|:40
LC66 -> - - - * * - - - - - - - - - * - | - - - - * * | <-- |74181:47|:41
LC65 -> - - - * * - - - - - - - - - * - | - - - - * * | <-- |74181:47|:42
LC74 -> - - - * * - - - - - - - - * - - | - - - - * * | <-- |74181:47|:49
LC71 -> - - - * * - - - - - - - - * - - | - - - - * * | <-- |74181:47|:50
Pin
8 -> * - - - - - - - - - - - - - - - | - - - * * - | <-- ALU_BUS
20 -> - - - * * - - - - - - - - - - - | - - - - * * | <-- CN
12 -> - - - * * - - - - - - - - - - - | - - - - * * | <-- M
68 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN001
17 -> * - - - - - - - - - - - - - - - | - - - * * - | <-- R4_BUS
47 -> * - - - - - - - - - - - - - - - | - - - * * - | <-- R5_BUS
7 -> * - - - - - - - - - - - - - - - | - - - * * - | <-- SW_BUS
25 -> - * - - - * - * - * - - * - - - | - - - - * * | <-- s0
14 -> - * - - - * - * - * - - * - - - | - - - - * * | <-- s1
23 -> - - * - - - * - * - * * - * * * | - - - - * * | <-- s2
4 -> - - * - - - * - * - * * - * * * | - - - - * * | <-- s3
LC93 -> - - - - - - - - - - - - - * - - | - - - - * - | <-- |74181:47|:76
LC91 -> - - - - - - - - - - - - - - - * | - - - - * - | <-- |74181:47|:88
LC89 -> - - - - - - - - - - - - - - * - | - - - - * - | <-- |74181:47|:89
LC34 -> - * * - - - - - - - - - - - - - | - - - - * - | <-- |74273:44|Q5
LC21 -> - - - - - - - - - - - * * * - - | - - - - * - | <-- |74273:44|Q4
LC20 -> - - - - - - - - - * * - - - * - | - - - - * - | <-- |74273:44|Q3
LC24 -> - - - - - - - * * - - - - - - * | - - - - * - | <-- |74273:44|Q2
LC22 -> - - - - - * * - - - - - - - - - | - - - - * - | <-- |74273:44|Q1
LC46 -> - * * - - - - - - - - - - - - - | - - - - * - | <-- |74273:45|Q5
LC28 -> - - - - - - - - - - - * * * - - | - - - - * - | <-- |74273:45|Q4
LC30 -> - - - - - - - - - * * - - - * - | - - - - * - | <-- |74273:45|Q3
LC32 -> - - - - - - - * * - - - - - - * | - - - - * - | <-- |74273:45|Q2
LC29 -> - - - - - * * - - - - - - - - - | - - - - * - | <-- |74273:45|Q1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\xyq\maxplus\sy4\fuheys.rpt
fuheys
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+------------------------------- LC81 CN4
| +----------------------------- LC84 |74181:46|:39
| | +--------------------------- LC82 |74181:46|:40
| | | +------------------------- LC83 |74181:46|:41
| | | | +----------------------- LC90 |74181:46|:42
| | | | | +--------------------- LC92 |74181:46|:49
| | | | | | +------------------- LC87 |74181:46|:50
| | | | | | | +----------------- LC96 |74181:46|:76
| | | | | | | | +--------------- LC95 |74181:46|F3N
| | | | | | | | | +------------- LC86 |74181:46|F2N
| | | | | | | | | | +----------- LC88 |74181:46|F1N
| | | | | | | | | | | +--------- LC94 |74181:46|:89
| | | | | | | | | | | | +------- LC93 |74181:47|:76
| | | | | | | | | | | | | +----- LC85 |74181:47|F0N
| | | | | | | | | | | | | | +--- LC91 |74181:47|:88
| | | | | | | | | | | | | | | +- LC89 |74181:47|:89
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'F':
LC84 -> * - - - - - - * - - * * - - - - | - - - - - * | <-- |74181:46|:39
LC82 -> * - - - - - - * - - * * - - - - | - - - - - * | <-- |74181:46|:40
LC83 -> * - - - - - - * - * - - - - - - | - - - - - * | <-- |74181:46|:41
LC90 -> * - - - - - - * - * - - - - - - | - - - - - * | <-- |74181:46|:42
LC92 -> * - - - - - - - * - - - - - - - | - - - - - * | <-- |74181:46|:49
LC87 -> * - - - - - - - * - - - - - - - | - - - - - * | <-- |74181:46|:50
LC96 -> - - - - - - - - * - - - - - - - | - - - - - * | <-- |74181:46|:76
LC94 -> - - - - - - - - - * - - - - - - | - - - - - * | <-- |74181:46|:89
Pin
20 -> * - - - - - - * - - - * * * * * | - - - - * * | <-- CN
12 -> - - - - - - - * - - - * * * * * | - - - - * * | <-- M
68 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- ~PIN001
25 -> - * - * - - * - - - - - - - - - | - - - - * * | <-- s0
14 -> - * - * - - * - - - - - - - - - | - - - - * * | <-- s1
23 -> - - * - * * - - * * * - - - - - | - - - - * * | <-- s2
4 -> - - * - * * - - * * * - - - - - | - - - - * * | <-- s3
LC70 -> * - - - - - - * - - - * - - - - | - - - - * * | <-- |74181:46|:37
LC73 -> * - - - - - - * - - - * - - - - | - - - - * * | <-- |74181:46|:38
LC72 -> - - - - - - - - - - * - - - - - | - - - - - * | <-- |74181:46|:88
LC68 -> * - - - - - - * - - - * * * * * | - - - - * * | <-- |74181:47|:37
LC75 -> * - - - - - - * - - - * * * * * | - - - - * * | <-- |74181:47|:38
LC80 -> * - - - - - - * - - - * * - - * | - - - - * * | <-- |74181:47|:39
LC67 -> * - - - - - - * - - - * * - - * | - - - - * * | <-- |74181:47|:40
LC66 -> * - - - - - - * - - - * * - - - | - - - - * * | <-- |74181:47|:41
LC65 -> * - - - - - - * - - - * * - - - | - - - - * * | <-- |74181:47|:42
LC74 -> * - - - - - - * - - - * - - - - | - - - - * * | <-- |74181:47|:49
LC71 -> * - - - - - - * - - - * - - - - | - - - - * * | <-- |74181:47|:50
LC40 -> - - - - - * * - * - - - - - - - | - - - - - * | <-- |74273:44|Q8
LC41 -> - - - * * - - - - * - - - - - - | - - - - - * | <-- |74273:44|Q7
LC35 -> - * * - - - - - - - * - - - - - | - - - - - * | <-- |74273:44|Q6
LC48 -> - - - - - * * - * - - - - - - - | - - - - - * | <-- |74273:45|Q8
LC47 -> - - - * * - - - - * - - - - - - | - - - - - * | <-- |74273:45|Q7
LC39 -> - * * - - - - - - - * - - - - - | - - - - - * | <-- |74273:45|Q6
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
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