bed_7seg.fit

用verilog语言写的拔河游戏机

-- MAX+plus II Compiler Fit File      
-- Version 10.12 09/21/2001           
-- Compiled: 03/24/2008 15:25:02      

-- Copyright (C) 1988-2001 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "bed_7seg"
BEGIN

    DEVICE = "EPM7032LC44-6";

    "inn0"                         : INPUT_PIN  = 7      ; -- LC4
    "inn1"                         : INPUT_PIN  = 6      ; -- LC3
    "inn2"                         : INPUT_PIN  = 5      ; -- LC2
    "inn3"                         : INPUT_PIN  = 4      ; -- LC1
    "a"                            : OUTPUT_PIN = 38     ; -- LC20
    "b"                            : OUTPUT_PIN = 37     ; -- LC21
    "c"                            : OUTPUT_PIN = 36     ; -- LC22
    "d"                            : OUTPUT_PIN = 34     ; -- LC23
    "e"                            : OUTPUT_PIN = 39     ; -- LC19
    "f"                            : OUTPUT_PIN = 40     ; -- LC18
    "g"                            : OUTPUT_PIN = 41     ; -- LC17

END;

INTERNAL_INFO "bed_7seg"
BEGIN
	DEVICE = EPM7032LC44-6;
	LC20    : LORAX = "G16R0";
	LC21    : LORAX = "G30R0";
	LC22    : LORAX = "G31R0";
	LC23    : LORAX = "G32R0";
	LC19    : LORAX = "G15R0";
	LC18    : LORAX = "G14R0";
	LC17    : LORAX = "G13R0";
	OH0R0P4 : LORAX = "G43R0,PA20R0C1";
	OH1R0P5 : LORAX = "G44R0,PA19R0C1";
	OH2R0P6 : LORAX = "G45R0,PA22R0C1";
	OH3R0P7 : LORAX = "G46R0,PA24R0C1";
END;