bed_7seg.vhd

来自「用verilog语言写的拔河游戏机」· VHDL 代码 · 共 44 行

library ieee;
use ieee.std_logic_1164.all;
entity bcd_7seg is
    port(inn:in std_logic_vector(3 downto 0);
         a,b,c,d,e,f,g:out std_logic);
    end bcd_7seg;

architecture rt1 of bcd_7seg is
    signal output :std_logic_vector(6 downto 0);
begin
 display_process:process(inn)
 begin
   case inn is 
   when "0000"=>output<="0111111";
   when "0001"=>output<="0000110";
   when "0010"=>output<="1011011";
   when "0011"=>output<="1001111";
   when "0100"=>output<="1100110";
   when "0101"=>output<="1101101";
   when "0110"=>output<="1111101";
   when "0111"=>output<="0000111";
   when "1000"=>output<="1111111";
   when "1001"=>output<="1100111";
   when "1010"=>output<="1110111";
   when "1011"=>output<="1111100";
   when "1100"=>output<="1011000";
   when "1101"=>output<="1011110";
   when "1110"=>output<="1111011";
   when "1111"=>output<="1110001";
   when others=>output<="0000000";
end case;
end process display_process;
a<=output(0);
b<=output(1);
c<=output(2);
d<=output(3);
e<=output(4);
f<=output(5);
g<=output(6);
end rt1;