📄 shiyan3gai.rpt
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-- Node name is '|74244:4|~6~1~3~2'
-- Equation name is '_LC7_D4', type is buried
-- synthesized logic cell
_LC7_D4 = LCELL( _EQ060);
_EQ060 = _LC4_D12 & sw_bus
# pc_bus & sw_bus
# _LC4_D12 & _LC6_D4
# _LC6_D4 & pc_bus;
-- Node name is '|74244:4|~6~1~3'
-- Equation name is '_LC8_D4', type is buried
_LC8_D4 = LCELL( _EQ061);
_EQ061 = _EC5_D & _LC7_D4
# _LC7_D4 & !MEMENAB
# _LC7_D4 & !RD;
-- Node name is '|74244:4|~10~1~3~2'
-- Equation name is '_LC5_D12', type is buried
-- synthesized logic cell
_LC5_D12 = LCELL( _EQ062);
_EQ062 = _LC8_D12 & sw_bus
# pc_bus & sw_bus
# _LC1_D4 & _LC8_D12
# _LC1_D4 & pc_bus;
-- Node name is '|74244:4|~10~1~3'
-- Equation name is '_LC2_D8', type is buried
_LC2_D8 = LCELL( _EQ063);
_EQ063 = _EC2_D & _LC5_D12
# _LC5_D12 & !MEMENAB
# _LC5_D12 & !RD;
-- Node name is '|74244:4|~11~1~3~2'
-- Equation name is '_LC6_D3', type is buried
-- synthesized logic cell
_LC6_D3 = LCELL( _EQ064);
_EQ064 = _LC2_D12 & sw_bus
# pc_bus & sw_bus
# _LC2_D12 & _LC8_D10
# _LC8_D10 & pc_bus;
-- Node name is '|74244:4|~11~1~3'
-- Equation name is '_LC3_D3', type is buried
_LC3_D3 = LCELL( _EQ065);
_EQ065 = _EC7_D & _LC6_D3
# _LC6_D3 & !MEMENAB
# _LC6_D3 & !RD;
-- Node name is '|74244:4|~26~1~3~2'
-- Equation name is '_LC1_D2', type is buried
-- synthesized logic cell
_LC1_D2 = LCELL( _EQ066);
_EQ066 = _LC4_D5 & sw_bus
# pc_bus & sw_bus
# _LC4_D5 & _LC6_D10
# _LC6_D10 & pc_bus;
-- Node name is '|74244:4|~26~1~3'
-- Equation name is '_LC3_D2', type is buried
_LC3_D2 = LCELL( _EQ067);
_EQ067 = _EC4_D & _LC1_D2
# _LC1_D2 & !MEMENAB
# _LC1_D2 & !RD;
-- Node name is '|74244:4|~27~1~3~2'
-- Equation name is '_LC3_D4', type is buried
-- synthesized logic cell
_LC3_D4 = LCELL( _EQ068);
_EQ068 = _LC3_D5 & sw_bus
# pc_bus & sw_bus
# _LC3_D5 & _LC4_D10
# _LC4_D10 & pc_bus;
-- Node name is '|74244:4|~27~1~3'
-- Equation name is '_LC2_D4', type is buried
_LC2_D4 = LCELL( _EQ069);
_EQ069 = _EC8_D & _LC3_D4
# _LC3_D4 & !MEMENAB
# _LC3_D4 & !RD;
-- Node name is '|74244:4|~31~1~3~2'
-- Equation name is '_LC4_D3', type is buried
-- synthesized logic cell
_LC4_D3 = LCELL( _EQ070);
_EQ070 = _LC2_D5 & sw_bus
# pc_bus & sw_bus
# _LC2_D5 & _LC2_D10
# _LC2_D10 & pc_bus;
-- Node name is '|74244:4|~31~1~3'
-- Equation name is '_LC2_D3', type is buried
_LC2_D3 = LCELL( _EQ071);
_EQ071 = _EC1_D & _LC4_D3
# _LC4_D3 & !MEMENAB
# _LC4_D3 & !RD;
-- Node name is '|74244:4|~36~1~3~2'
-- Equation name is '_LC5_D8', type is buried
-- synthesized logic cell
_LC5_D8 = LCELL( _EQ072);
_EQ072 = _LC1_D5 & sw_bus
# pc_bus & sw_bus
# _LC1_D5 & _LC3_D10
# _LC3_D10 & pc_bus;
-- Node name is '|74244:4|~36~1~3'
-- Equation name is '_LC1_D8', type is buried
_LC1_D8 = LCELL( _EQ073);
_EQ073 = _EC3_D & _LC5_D8
# _LC5_D8 & !MEMENAB
# _LC5_D8 & !RD;
-- Node name is '|74273:5|:19' = '|74273:5|Q1'
-- Equation name is '_LC5_D7', type is buried
_LC5_D7 = DFFE( _LC3_D12, _LC4_D7, VCC, VCC, VCC);
-- Node name is '|74273:5|:18' = '|74273:5|Q2'
-- Equation name is '_LC6_D7', type is buried
_LC6_D7 = DFFE( _LC4_D12, _LC4_D7, VCC, VCC, VCC);
-- Node name is '|74273:5|:17' = '|74273:5|Q3'
-- Equation name is '_LC6_D12', type is buried
_LC6_D12 = DFFE( _LC8_D12, _LC4_D7, VCC, VCC, VCC);
-- Node name is '|74273:5|:16' = '|74273:5|Q4'
-- Equation name is '_LC1_D7', type is buried
_LC1_D7 = DFFE( _LC2_D12, _LC4_D7, VCC, VCC, VCC);
-- Node name is '|74273:5|:15' = '|74273:5|Q5'
-- Equation name is '_LC3_D7', type is buried
_LC3_D7 = DFFE( _LC1_D5, _LC4_D7, VCC, VCC, VCC);
-- Node name is '|74273:5|:14' = '|74273:5|Q6'
-- Equation name is '_LC5_D3', type is buried
_LC5_D3 = DFFE( _LC2_D5, _LC4_D7, VCC, VCC, VCC);
-- Node name is '|74273:5|:13' = '|74273:5|Q7'
-- Equation name is '_LC8_D7', type is buried
_LC8_D7 = DFFE( _LC3_D5, _LC4_D7, VCC, VCC, VCC);
-- Node name is '|74273:5|:12' = '|74273:5|Q8'
-- Equation name is '_LC2_D7', type is buried
_LC2_D7 = DFFE( _LC4_D5, _LC4_D7, VCC, VCC, VCC);
-- Node name is ':27'
-- Equation name is '_LC4_D7', type is buried
_LC4_D7 = LCELL( _EQ074);
_EQ074 = !cp161ldar & LDAR;
-- Node name is ':32'
-- Equation name is '_LC7_D10', type is buried
_LC7_D10 = LCELL( _EQ075);
_EQ075 = clk_cdu & 161pc;
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_0' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC6_D', type is memory
_EC6_D = MEMORY_SEGMENT( d0, clk_cdu, VCC, _LC3_D8, VCC, _LC5_D7, _LC6_D7, _LC6_D12, _LC1_D7, _LC3_D7, _LC5_D3, _LC8_D7, _LC2_D7, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_1' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC5_D', type is memory
_EC5_D = MEMORY_SEGMENT( d1, clk_cdu, VCC, _LC3_D8, VCC, _LC5_D7, _LC6_D7, _LC6_D12, _LC1_D7, _LC3_D7, _LC5_D3, _LC8_D7, _LC2_D7, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_2' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC2_D', type is memory
_EC2_D = MEMORY_SEGMENT( d2, clk_cdu, VCC, _LC3_D8, VCC, _LC5_D7, _LC6_D7, _LC6_D12, _LC1_D7, _LC3_D7, _LC5_D3, _LC8_D7, _LC2_D7, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_3' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC7_D', type is memory
_EC7_D = MEMORY_SEGMENT( d3, clk_cdu, VCC, _LC3_D8, VCC, _LC5_D7, _LC6_D7, _LC6_D12, _LC1_D7, _LC3_D7, _LC5_D3, _LC8_D7, _LC2_D7, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_4' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC3_D', type is memory
_EC3_D = MEMORY_SEGMENT( d4, clk_cdu, VCC, _LC3_D8, VCC, _LC5_D7, _LC6_D7, _LC6_D12, _LC1_D7, _LC3_D7, _LC5_D3, _LC8_D7, _LC2_D7, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_5' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC1_D', type is memory
_EC1_D = MEMORY_SEGMENT( d5, clk_cdu, VCC, _LC3_D8, VCC, _LC5_D7, _LC6_D7, _LC6_D12, _LC1_D7, _LC3_D7, _LC5_D3, _LC8_D7, _LC2_D7, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_6' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC8_D', type is memory
_EC8_D = MEMORY_SEGMENT( d6, clk_cdu, VCC, _LC3_D8, VCC, _LC5_D7, _LC6_D7, _LC6_D12, _LC1_D7, _LC3_D7, _LC5_D3, _LC8_D7, _LC2_D7, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:57|altram:sram|segment0_7' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC4_D', type is memory
_EC4_D = MEMORY_SEGMENT( d7, clk_cdu, VCC, _LC3_D8, VCC, _LC5_D7, _LC6_D7, _LC6_D12, _LC1_D7, _LC3_D7, _LC5_D3, _LC8_D7, _LC2_D7, VCC, VCC, VCC,);
Project Information d:\shiyan3\shiyan3gai.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,401K
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